//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
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//-----------------------------------------------------------------------------
//
// Project    : Ultrascale FPGA Gen3 Integrated Block for PCI Express
// File       : xdma_x8gen3_pcie3_ip_pcie3_uscale_wrapper.v
// Version    : 4.4 
//-----------------------------------------------------------------------------

/////////////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module xdma_x8gen3_pcie3_ip_pcie3_uscale_wrapper 
#(
  parameter TCQ = 100,
  parameter NO_DECODE_LOGIC  = "TRUE",
  parameter INTERFACE_SPEED  = "500MHZ",
  parameter COMPLETION_SPACE = "16KB",
  parameter ARI_CAP_ENABLE = "FALSE",
  parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE",
  parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
  parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000,
  parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
  parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
  parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
  parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE",
  parameter [1:0] AXISTEN_IF_WIDTH = 2'h2,
  parameter CRM_CORE_CLK_FREQ_500 = "TRUE",
  parameter [1:0] CRM_USER_CLK_FREQ = 2'h2,
  parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE",
  parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
  parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE",
  parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
  parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
  parameter LL_ACK_TIMEOUT_EN = "FALSE",
  parameter integer LL_ACK_TIMEOUT_FUNC = 0,
  parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
  parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
  parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
  parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
  parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
  parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0fa,
  parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
  parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
  parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000,
  parameter MCAP_CONFIGURE_OVERRIDE = "FALSE",
  parameter MCAP_ENABLE = "FALSE",
  parameter MCAP_EOS_DESIGN_SWITCH = "TRUE",
  parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000,
  parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "TRUE",
  parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "TRUE",
  parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE",
  parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE",
  parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE",
  parameter [15:0] MCAP_VSEC_ID = 16'h0000,
  parameter [11:0] MCAP_VSEC_LEN = 12'h02c,
  parameter [3:0] MCAP_VSEC_REV = 4'h0,
  parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
  parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF0_BIST_REGISTER = 8'h00,
  parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF0_CLASS_CODE = 24'h000000,
  parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
  parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
  parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
  parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
  parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE",
  parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
  parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
  parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
  parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
  parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
  parameter [15:0] PF0_DEVICE_ID = 16'h0000,
  parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
  parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
  parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
  parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
  parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
  parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
  parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
  parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
  parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF0_PB_CAP_VER = 4'h1,
  parameter [7:0] PF0_PM_CAP_ID = 8'h01,
  parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
  parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
  parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
  parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
  parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
  parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
  parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
  parameter PF0_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF0_RBAR_NUM = 3'h1,
  parameter [7:0] PF0_REVISION_ID = 8'h00,
  parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
  parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF0_TPHR_CAP_ENABLE = "FALSE",
  parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
  parameter PF0_VC_CAP_ENABLE = "FALSE",
  parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
  parameter [3:0] PF0_VC_CAP_VER = 4'h1,
  parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF1_BIST_REGISTER = 8'h00,
  parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF1_CLASS_CODE = 24'h000000,
  parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF1_DEVICE_ID = 16'h0000,
  parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
  parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
  parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF1_PB_CAP_VER = 4'h1,
  parameter [7:0] PF1_PM_CAP_ID = 8'h01,
  parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
  parameter PF1_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF1_RBAR_NUM = 3'h1,
  parameter [7:0] PF1_REVISION_ID = 8'h00,
  parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
  parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF1_TPHR_CAP_ENABLE = "FALSE",
  parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
  parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF2_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF2_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF2_BIST_REGISTER = 8'h00,
  parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF2_CLASS_CODE = 24'h000000,
  parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF2_DEVICE_ID = 16'h0000,
  parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF2_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF2_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF2_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF2_INTERRUPT_PIN = 3'h1,
  parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF2_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF2_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000,
  parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF2_PB_CAP_VER = 4'h1,
  parameter [7:0] PF2_PM_CAP_ID = 8'h01,
  parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3,
  parameter PF2_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF2_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF2_RBAR_NUM = 3'h1,
  parameter [7:0] PF2_REVISION_ID = 8'h00,
  parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000,
  parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF2_TPHR_CAP_ENABLE = "FALSE",
  parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF2_TPHR_CAP_VER = 4'h1,
  parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
  parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
  parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000,
  parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00,
  parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000,
  parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03,
  parameter [2:0] PF3_BAR0_CONTROL = 3'h4,
  parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00,
  parameter [2:0] PF3_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_BAR5_CONTROL = 3'h0,
  parameter [7:0] PF3_BIST_REGISTER = 8'h00,
  parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50,
  parameter [23:0] PF3_CLASS_CODE = 24'h000000,
  parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
  parameter [15:0] PF3_DEVICE_ID = 16'h0000,
  parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000,
  parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
  parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
  parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
  parameter [3:0] PF3_DPA_CAP_VER = 4'h1,
  parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10c,
  parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
  parameter PF3_EXPANSION_ROM_ENABLE = "FALSE",
  parameter [7:0] PF3_INTERRUPT_LINE = 8'h00,
  parameter [2:0] PF3_INTERRUPT_PIN = 3'h1,
  parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0,
  parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00,
  parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE",
  parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00,
  parameter integer PF3_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer PF3_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000,
  parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000,
  parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000,
  parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
  parameter [3:0] PF3_PB_CAP_VER = 4'h1,
  parameter [7:0] PF3_PM_CAP_ID = 8'h01,
  parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3,
  parameter PF3_RBAR_CAP_ENABLE = "FALSE",
  parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000,
  parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000,
  parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000,
  parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000,
  parameter [3:0] PF3_RBAR_CAP_VER = 4'h1,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0,
  parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00,
  parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00,
  parameter [2:0] PF3_RBAR_NUM = 3'h1,
  parameter [7:0] PF3_REVISION_ID = 8'h00,
  parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
  parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0,
  parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0,
  parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4,
  parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
  parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0,
  parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000,
  parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000,
  parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000,
  parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1,
  parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000,
  parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000,
  parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
  parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000,
  parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000,
  parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter PF3_TPHR_CAP_ENABLE = "FALSE",
  parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] PF3_TPHR_CAP_VER = 4'h1,
  parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE",
  parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE",
  parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
  parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
  parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "FALSE",
  parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE",
  parameter PL_DISABLE_SCRAMBLING = "FALSE",
  parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE",
  parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
  parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
  parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
  parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
  parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
  parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
  parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3,
  parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4,
  parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE",
  parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
  parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3f00,
  parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3f00,
  parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4,
  parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8,
  parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
  parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
  parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
  parameter integer PL_N_FTS_GEN1 = 255,
  parameter integer PL_N_FTS_GEN2 = 255,
  parameter integer PL_N_FTS_GEN3 = 255,
  parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE",
  parameter PL_SIM_FAST_LINK_TRAINING = "TRUE",
  parameter PL_UPSTREAM_FACING = "TRUE",
  parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05dc,
  parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000,
  parameter PM_ENABLE_L23_ENTRY = "FALSE",
  parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
  parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000,
  parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186a0,
  parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
  parameter SIM_JTAG_IDCODE = 32'h00000000,
  parameter SIM_VERSION = "1.0",
  parameter integer SPARE_BIT0 = 0,
  parameter integer SPARE_BIT1 = 0,
  parameter integer SPARE_BIT2 = 0,
  parameter integer SPARE_BIT3 = 0,
  parameter integer SPARE_BIT4 = 0,
  parameter integer SPARE_BIT5 = 0,
  parameter integer SPARE_BIT6 = 0,
  parameter integer SPARE_BIT7 = 0,
  parameter integer SPARE_BIT8 = 0,
  parameter [7:0] SPARE_BYTE0 = 8'h00,
  parameter [7:0] SPARE_BYTE1 = 8'h00,
  parameter [7:0] SPARE_BYTE2 = 8'h00,
  parameter [7:0] SPARE_BYTE3 = 8'h00,
  parameter [31:0] SPARE_WORD0 = 32'h00000000,
  parameter [31:0] SPARE_WORD1 = 32'h00000000,
  parameter [31:0] SPARE_WORD2 = 32'h00000000,
  parameter [31:0] SPARE_WORD3 = 32'h00000000,
  parameter SRIOV_CAP_ENABLE = "FALSE",
  parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE",
  parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hbebc20,
  parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2faf080,
  parameter [11:0] TL_CREDITS_CD = 12'h3e0,
  parameter [7:0] TL_CREDITS_CH = 8'h20,
  parameter [11:0] TL_CREDITS_NPD = 12'h028,
  parameter [7:0] TL_CREDITS_NPH = 8'h20,
  parameter [11:0] TL_CREDITS_PD = 12'h198,
  parameter [7:0] TL_CREDITS_PH = 8'h20,
  parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
  parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
  parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
  parameter TL_LEGACY_MODE_ENABLE = "FALSE",
  parameter [1:0] TL_PF_ENABLE_REG = 2'h0,
  parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE",
  parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE",
  parameter TWO_LAYER_MODE_ENABLE = "FALSE",
  parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE",
  parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
  parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
  parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF0_PM_CAP_ID = 8'h01,
  parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
  parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF0_TPHR_CAP_ENABLE = "FALSE",
  parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF1_PM_CAP_ID = 8'h01,
  parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
  parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF1_TPHR_CAP_ENABLE = "FALSE",
  parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF2_PM_CAP_ID = 8'h01,
  parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
  parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF2_TPHR_CAP_ENABLE = "FALSE",
  parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF3_PM_CAP_ID = 8'h01,
  parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
  parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF3_TPHR_CAP_ENABLE = "FALSE",
  parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF4_PM_CAP_ID = 8'h01,
  parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
  parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF4_TPHR_CAP_ENABLE = "FALSE",
  parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF5_PM_CAP_ID = 8'h01,
  parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
  parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF5_TPHR_CAP_ENABLE = "FALSE",
  parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF6_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF6_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF6_PM_CAP_ID = 8'h01,
  parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3,
  parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF6_TPHR_CAP_ENABLE = "FALSE",
  parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF6_TPHR_CAP_VER = 4'h1,
  parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000,
  parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0,
  parameter integer VF7_MSIX_CAP_PBA_BIR = 0,
  parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050,
  parameter integer VF7_MSIX_CAP_TABLE_BIR = 0,
  parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
  parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000,
  parameter [7:0] VF7_PM_CAP_ID = 8'h01,
  parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00,
  parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3,
  parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
  parameter VF7_TPHR_CAP_ENABLE = "FALSE",
  parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE",
  parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000,
  parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0,
  parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0,
  parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
  parameter [3:0] VF7_TPHR_CAP_VER = 4'h1
  ) (
  input  wire         CFGCONFIGSPACEENABLE,
  input  wire  [15:0] CFGDEVID,
  input  wire   [7:0] CFGDSBUSNUMBER,
  input  wire   [4:0] CFGDSDEVICENUMBER,
  input  wire   [2:0] CFGDSFUNCTIONNUMBER,
  input  wire  [63:0] CFGDSN,
  input  wire   [7:0] CFGDSPORTNUMBER,
  input  wire         CFGERRCORIN,
  input  wire         CFGERRUNCORIN,
  input  wire  [31:0] CFGEXTREADDATA,
  input  wire         CFGEXTREADDATAVALID,
  input  wire   [2:0] CFGFCSEL,
  input  wire   [3:0] CFGFLRDONE,
  input  wire         CFGHOTRESETIN,
  input  wire   [3:0] CFGINTERRUPTINT,
  input  wire   [2:0] CFGINTERRUPTMSIATTR,
  input  wire   [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER,
  input  wire  [31:0] CFGINTERRUPTMSIINT,
  input  wire  [31:0] CFGINTERRUPTMSIPENDINGSTATUS,
  input  wire         CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE,
  input  wire   [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM,
  input  wire   [3:0] CFGINTERRUPTMSISELECT,
  input  wire         CFGINTERRUPTMSITPHPRESENT,
  input  wire   [8:0] CFGINTERRUPTMSITPHSTTAG,
  input  wire   [1:0] CFGINTERRUPTMSITPHTYPE,
  input  wire  [63:0] CFGINTERRUPTMSIXADDRESS,
  input  wire  [31:0] CFGINTERRUPTMSIXDATA,
  input  wire         CFGINTERRUPTMSIXINT,
  input  wire   [3:0] CFGINTERRUPTPENDING,
  input  wire         CFGLINKTRAININGENABLE,
  input  wire  [18:0] CFGMGMTADDR,
  input  wire   [3:0] CFGMGMTBYTEENABLE,
  input  wire         CFGMGMTREAD,
  input  wire         CFGMGMTTYPE1CFGREGACCESS,
  input  wire         CFGMGMTWRITE,
  input  wire  [31:0] CFGMGMTWRITEDATA,
  input  wire         CFGMSGTRANSMIT,
  input  wire  [31:0] CFGMSGTRANSMITDATA,
  input  wire   [2:0] CFGMSGTRANSMITTYPE,
  input  wire   [2:0] CFGPERFUNCSTATUSCONTROL,
  input  wire   [3:0] CFGPERFUNCTIONNUMBER,
  input  wire         CFGPERFUNCTIONOUTPUTREQUEST,
  input  wire         CFGPOWERSTATECHANGEACK,
  input  wire         CFGREQPMTRANSITIONL23READY,
  input  wire   [7:0] CFGREVID,
  input  wire  [15:0] CFGSUBSYSID,
  input  wire  [15:0] CFGSUBSYSVENDID,
  input  wire  [31:0] CFGTPHSTTREADDATA,
  input  wire         CFGTPHSTTREADDATAVALID,
  input  wire  [15:0] CFGVENDID,
  input  wire   [7:0] CFGVFFLRDONE,
  input  wire         CONFMCAPREQUESTBYCONF,
  input  wire  [31:0] CONFREQDATA,
  input  wire   [3:0] CONFREQREGNUM,
  input  wire   [1:0] CONFREQTYPE,
  input  wire         CONFREQVALID,
  input  wire         CORECLK,
  input  wire         CORECLKMICOMPLETIONRAML,
  input  wire         CORECLKMICOMPLETIONRAMU,
  input  wire         CORECLKMIREPLAYRAM,
  input  wire         CORECLKMIREQUESTRAM,
  input  wire         DBGCFGLOCALMGMTREGOVERRIDE,
  input  wire   [3:0] DBGDATASEL,
  input  wire   [9:0] DRPADDR,
  input  wire         DRPCLK,
  input  wire  [15:0] DRPDI,
  input  wire         DRPEN,
  input  wire         DRPWE,
  input  wire  [13:0] LL2LMSAXISTXTUSER,
  input  wire         LL2LMSAXISTXTVALID,
  input  wire   [3:0] LL2LMTXTLPID0,
  input  wire   [3:0] LL2LMTXTLPID1,
  input  wire  [21:0] MAXISCQTREADY,
  input  wire  [21:0] MAXISRCTREADY,
  input  wire         MCAPCLK,
  input  wire         MCAPPERST0B,
  input  wire         MCAPPERST1B,
  input  wire         MGMTRESETN,
  input  wire         MGMTSTICKYRESETN,
  input  wire         PCIECQNPREQ,
  input  wire         PIPECLK,
  input  wire   [5:0] PIPEEQFS,
  input  wire   [5:0] PIPEEQLF,
  input  wire         PIPERESETN,
  input  wire   [1:0] PIPERX0CHARISK,
  input  wire  [31:0] PIPERX0DATA,
  input  wire         PIPERX0DATAVALID,
  input  wire         PIPERX0ELECIDLE,
  input  wire         PIPERX0EQDONE,
  input  wire         PIPERX0EQLPADAPTDONE,
  input  wire         PIPERX0EQLPLFFSSEL,
  input  wire  [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX0PHYSTATUS,
  input  wire         PIPERX0STARTBLOCK,
  input  wire   [2:0] PIPERX0STATUS,
  input  wire   [1:0] PIPERX0SYNCHEADER,
  input  wire         PIPERX0VALID,
  input  wire   [1:0] PIPERX1CHARISK,
  input  wire  [31:0] PIPERX1DATA,
  input  wire         PIPERX1DATAVALID,
  input  wire         PIPERX1ELECIDLE,
  input  wire         PIPERX1EQDONE,
  input  wire         PIPERX1EQLPADAPTDONE,
  input  wire         PIPERX1EQLPLFFSSEL,
  input  wire  [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX1PHYSTATUS,
  input  wire         PIPERX1STARTBLOCK,
  input  wire   [2:0] PIPERX1STATUS,
  input  wire   [1:0] PIPERX1SYNCHEADER,
  input  wire         PIPERX1VALID,
  input  wire   [1:0] PIPERX2CHARISK,
  input  wire  [31:0] PIPERX2DATA,
  input  wire         PIPERX2DATAVALID,
  input  wire         PIPERX2ELECIDLE,
  input  wire         PIPERX2EQDONE,
  input  wire         PIPERX2EQLPADAPTDONE,
  input  wire         PIPERX2EQLPLFFSSEL,
  input  wire  [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX2PHYSTATUS,
  input  wire         PIPERX2STARTBLOCK,
  input  wire   [2:0] PIPERX2STATUS,
  input  wire   [1:0] PIPERX2SYNCHEADER,
  input  wire         PIPERX2VALID,
  input  wire   [1:0] PIPERX3CHARISK,
  input  wire  [31:0] PIPERX3DATA,
  input  wire         PIPERX3DATAVALID,
  input  wire         PIPERX3ELECIDLE,
  input  wire         PIPERX3EQDONE,
  input  wire         PIPERX3EQLPADAPTDONE,
  input  wire         PIPERX3EQLPLFFSSEL,
  input  wire  [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX3PHYSTATUS,
  input  wire         PIPERX3STARTBLOCK,
  input  wire   [2:0] PIPERX3STATUS,
  input  wire   [1:0] PIPERX3SYNCHEADER,
  input  wire         PIPERX3VALID,
  input  wire   [1:0] PIPERX4CHARISK,
  input  wire  [31:0] PIPERX4DATA,
  input  wire         PIPERX4DATAVALID,
  input  wire         PIPERX4ELECIDLE,
  input  wire         PIPERX4EQDONE,
  input  wire         PIPERX4EQLPADAPTDONE,
  input  wire         PIPERX4EQLPLFFSSEL,
  input  wire  [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX4PHYSTATUS,
  input  wire         PIPERX4STARTBLOCK,
  input  wire   [2:0] PIPERX4STATUS,
  input  wire   [1:0] PIPERX4SYNCHEADER,
  input  wire         PIPERX4VALID,
  input  wire   [1:0] PIPERX5CHARISK,
  input  wire  [31:0] PIPERX5DATA,
  input  wire         PIPERX5DATAVALID,
  input  wire         PIPERX5ELECIDLE,
  input  wire         PIPERX5EQDONE,
  input  wire         PIPERX5EQLPADAPTDONE,
  input  wire         PIPERX5EQLPLFFSSEL,
  input  wire  [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX5PHYSTATUS,
  input  wire         PIPERX5STARTBLOCK,
  input  wire   [2:0] PIPERX5STATUS,
  input  wire   [1:0] PIPERX5SYNCHEADER,
  input  wire         PIPERX5VALID,
  input  wire   [1:0] PIPERX6CHARISK,
  input  wire  [31:0] PIPERX6DATA,
  input  wire         PIPERX6DATAVALID,
  input  wire         PIPERX6ELECIDLE,
  input  wire         PIPERX6EQDONE,
  input  wire         PIPERX6EQLPADAPTDONE,
  input  wire         PIPERX6EQLPLFFSSEL,
  input  wire  [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX6PHYSTATUS,
  input  wire         PIPERX6STARTBLOCK,
  input  wire   [2:0] PIPERX6STATUS,
  input  wire   [1:0] PIPERX6SYNCHEADER,
  input  wire         PIPERX6VALID,
  input  wire   [1:0] PIPERX7CHARISK,
  input  wire  [31:0] PIPERX7DATA,
  input  wire         PIPERX7DATAVALID,
  input  wire         PIPERX7ELECIDLE,
  input  wire         PIPERX7EQDONE,
  input  wire         PIPERX7EQLPADAPTDONE,
  input  wire         PIPERX7EQLPLFFSSEL,
  input  wire  [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET,
  input  wire         PIPERX7PHYSTATUS,
  input  wire         PIPERX7STARTBLOCK,
  input  wire   [2:0] PIPERX7STATUS,
  input  wire   [1:0] PIPERX7SYNCHEADER,
  input  wire         PIPERX7VALID,
  input  wire  [17:0] PIPETX0EQCOEFF,
  input  wire         PIPETX0EQDONE,
  input  wire  [17:0] PIPETX1EQCOEFF,
  input  wire         PIPETX1EQDONE,
  input  wire  [17:0] PIPETX2EQCOEFF,
  input  wire         PIPETX2EQDONE,
  input  wire  [17:0] PIPETX3EQCOEFF,
  input  wire         PIPETX3EQDONE,
  input  wire  [17:0] PIPETX4EQCOEFF,
  input  wire         PIPETX4EQDONE,
  input  wire  [17:0] PIPETX5EQCOEFF,
  input  wire         PIPETX5EQDONE,
  input  wire  [17:0] PIPETX6EQCOEFF,
  input  wire         PIPETX6EQDONE,
  input  wire  [17:0] PIPETX7EQCOEFF,
  input  wire         PIPETX7EQDONE,
  input  wire         PLEQRESETEIEOSCOUNT,
  input  wire         PLGEN2UPSTREAMPREFERDEEMPH,
  input  wire         RESETN,
  input  wire [255:0] SAXISCCTDATA,
  input  wire   [7:0] SAXISCCTKEEP,
  input  wire         SAXISCCTLAST,
  input  wire  [32:0] SAXISCCTUSER,
  input  wire         SAXISCCTVALID,
  input  wire [255:0] SAXISRQTDATA,
  input  wire   [7:0] SAXISRQTKEEP,
  input  wire         SAXISRQTLAST,
  input  wire  [59:0] SAXISRQTUSER,
  input  wire         SAXISRQTVALID,
  input  wire  [31:0] SPAREIN,
  input  wire         USERCLK,
  output wire   [2:0] CFGCURRENTSPEED,
  output wire   [3:0] CFGDPASUBSTATECHANGE,
  output wire         CFGERRCOROUT,
  output wire         CFGERRFATALOUT,
  output wire         CFGERRNONFATALOUT,
  output wire   [7:0] CFGEXTFUNCTIONNUMBER,
  output wire         CFGEXTREADRECEIVED,
  output wire   [9:0] CFGEXTREGISTERNUMBER,
  output wire   [3:0] CFGEXTWRITEBYTEENABLE,
  output wire  [31:0] CFGEXTWRITEDATA,
  output wire         CFGEXTWRITERECEIVED,
  output wire  [11:0] CFGFCCPLD,
  output wire   [7:0] CFGFCCPLH,
  output wire  [11:0] CFGFCNPD,
  output wire   [7:0] CFGFCNPH,
  output wire  [11:0] CFGFCPD,
  output wire   [7:0] CFGFCPH,
  output wire   [3:0] CFGFLRINPROCESS,
  output wire  [11:0] CFGFUNCTIONPOWERSTATE,
  output wire  [15:0] CFGFUNCTIONSTATUS,
  output wire         CFGHOTRESETOUT,
  output wire  [31:0] CFGINTERRUPTMSIDATA,
  output wire   [3:0] CFGINTERRUPTMSIENABLE,
  output wire         CFGINTERRUPTMSIFAIL,
  output wire         CFGINTERRUPTMSIMASKUPDATE,
  output wire  [11:0] CFGINTERRUPTMSIMMENABLE,
  output wire         CFGINTERRUPTMSISENT,
  output wire   [7:0] CFGINTERRUPTMSIVFENABLE,
  output wire   [3:0] CFGINTERRUPTMSIXENABLE,
  output wire         CFGINTERRUPTMSIXFAIL,
  output wire   [3:0] CFGINTERRUPTMSIXMASK,
  output wire         CFGINTERRUPTMSIXSENT,
  output wire   [7:0] CFGINTERRUPTMSIXVFENABLE,
  output wire   [7:0] CFGINTERRUPTMSIXVFMASK,
  output wire         CFGINTERRUPTSENT,
  output wire   [1:0] CFGLINKPOWERSTATE,
  output wire         CFGLOCALERROR,
  output wire         CFGLTRENABLE,
  output wire   [5:0] CFGLTSSMSTATE,
  output wire   [2:0] CFGMAXPAYLOAD,
  output wire   [2:0] CFGMAXREADREQ,
  output wire  [31:0] CFGMGMTREADDATA,
  output wire         CFGMGMTREADWRITEDONE,
  output wire         CFGMSGRECEIVED,
  output wire   [7:0] CFGMSGRECEIVEDDATA,
  output wire   [4:0] CFGMSGRECEIVEDTYPE,
  output wire         CFGMSGTRANSMITDONE,
  output wire   [3:0] CFGNEGOTIATEDWIDTH,
  output wire   [1:0] CFGOBFFENABLE,
  output wire  [15:0] CFGPERFUNCSTATUSDATA,
  output wire         CFGPERFUNCTIONUPDATEDONE,
  output wire         CFGPHYLINKDOWN,
  output wire   [1:0] CFGPHYLINKSTATUS,
  output wire         CFGPLSTATUSCHANGE,
  output wire         CFGPOWERSTATECHANGEINTERRUPT,
  output wire   [3:0] CFGRCBSTATUS,
  output wire   [3:0] CFGTPHFUNCTIONNUM,
  output wire   [3:0] CFGTPHREQUESTERENABLE,
  output wire  [11:0] CFGTPHSTMODE,
  output wire   [4:0] CFGTPHSTTADDRESS,
  output wire         CFGTPHSTTREADENABLE,
  output wire   [3:0] CFGTPHSTTWRITEBYTEVALID,
  output wire  [31:0] CFGTPHSTTWRITEDATA,
  output wire         CFGTPHSTTWRITEENABLE,
  output wire   [7:0] CFGVFFLRINPROCESS,
  output wire  [23:0] CFGVFPOWERSTATE,
  output wire  [15:0] CFGVFSTATUS,
  output wire   [7:0] CFGVFTPHREQUESTERENABLE,
  output wire  [23:0] CFGVFTPHSTMODE,
  output wire         CONFMCAPDESIGNSWITCH,
  output wire         CONFMCAPEOS,
  output wire         CONFMCAPINUSEBYPCIE,
  output wire         CONFREQREADY,
  output wire  [31:0] CONFRESPRDATA,
  output wire         CONFRESPVALID,
  output wire  [15:0] DBGDATAOUT,
  output wire         DBGMCAPCSB,
  output wire  [31:0] DBGMCAPDATA,
  output wire         DBGMCAPEOS,
  output wire         DBGMCAPERROR,
  output wire         DBGMCAPMODE,
  output wire         DBGMCAPRDATAVALID,
  output wire         DBGMCAPRDWRB,
  output wire         DBGMCAPRESET,
  output wire         DBGPLDATABLOCKRECEIVEDAFTEREDS,
  output wire         DBGPLGEN3FRAMINGERRORDETECTED,
  output wire         DBGPLGEN3SYNCHEADERERRORDETECTED,
  output wire   [7:0] DBGPLINFERREDRXELECTRICALIDLE,
  output wire  [15:0] DRPDO,
  output wire         DRPRDY,
  output wire   [3:0] LL2LMMASTERTLPSENTTLPID0,
  output wire   [3:0] LL2LMMASTERTLPSENTTLPID1,
  output wire         LL2LMMASTERTLPSENT0,
  output wire         LL2LMMASTERTLPSENT1,
  output wire [255:0] LL2LMMAXISRXTDATA,
  output wire  [17:0] LL2LMMAXISRXTUSER,
  output wire   [7:0] LL2LMMAXISRXTVALID,
  output wire   [7:0] LL2LMSAXISTXTREADY,
  output wire [255:0] MAXISCQTDATA,
  output wire   [7:0] MAXISCQTKEEP,
  output wire         MAXISCQTLAST,
  output wire  [84:0] MAXISCQTUSER,
  output wire         MAXISCQTVALID,
  output wire [255:0] MAXISRCTDATA,
  output wire   [7:0] MAXISRCTKEEP,
  output wire         MAXISRCTLAST,
  output wire  [74:0] MAXISRCTUSER,
  output wire         MAXISRCTVALID,
  output wire   [5:0] PCIECQNPREQCOUNT,
  output wire         PCIEPERST0B,
  output wire         PCIEPERST1B,
  output wire   [3:0] PCIERQSEQNUM,
  output wire         PCIERQSEQNUMVLD,
  output wire   [5:0] PCIERQTAG,
  output wire   [1:0] PCIERQTAGAV,
  output wire         PCIERQTAGVLD,
  output wire   [1:0] PCIETFCNPDAV,
  output wire   [1:0] PCIETFCNPHAV,
  output wire   [1:0] PIPERX0EQCONTROL,
  output wire   [5:0] PIPERX0EQLPLFFS,
  output wire   [3:0] PIPERX0EQLPTXPRESET,
  output wire   [2:0] PIPERX0EQPRESET,
  output wire         PIPERX0POLARITY,
  output wire   [1:0] PIPERX1EQCONTROL,
  output wire   [5:0] PIPERX1EQLPLFFS,
  output wire   [3:0] PIPERX1EQLPTXPRESET,
  output wire   [2:0] PIPERX1EQPRESET,
  output wire         PIPERX1POLARITY,
  output wire   [1:0] PIPERX2EQCONTROL,
  output wire   [5:0] PIPERX2EQLPLFFS,
  output wire   [3:0] PIPERX2EQLPTXPRESET,
  output wire   [2:0] PIPERX2EQPRESET,
  output wire         PIPERX2POLARITY,
  output wire   [1:0] PIPERX3EQCONTROL,
  output wire   [5:0] PIPERX3EQLPLFFS,
  output wire   [3:0] PIPERX3EQLPTXPRESET,
  output wire   [2:0] PIPERX3EQPRESET,
  output wire         PIPERX3POLARITY,
  output wire   [1:0] PIPERX4EQCONTROL,
  output wire   [5:0] PIPERX4EQLPLFFS,
  output wire   [3:0] PIPERX4EQLPTXPRESET,
  output wire   [2:0] PIPERX4EQPRESET,
  output wire         PIPERX4POLARITY,
  output wire   [1:0] PIPERX5EQCONTROL,
  output wire   [5:0] PIPERX5EQLPLFFS,
  output wire   [3:0] PIPERX5EQLPTXPRESET,
  output wire   [2:0] PIPERX5EQPRESET,
  output wire         PIPERX5POLARITY,
  output wire   [1:0] PIPERX6EQCONTROL,
  output wire   [5:0] PIPERX6EQLPLFFS,
  output wire   [3:0] PIPERX6EQLPTXPRESET,
  output wire   [2:0] PIPERX6EQPRESET,
  output wire         PIPERX6POLARITY,
  output wire   [1:0] PIPERX7EQCONTROL,
  output wire   [5:0] PIPERX7EQLPLFFS,
  output wire   [3:0] PIPERX7EQLPTXPRESET,
  output wire   [2:0] PIPERX7EQPRESET,
  output wire         PIPERX7POLARITY,
  output wire   [1:0] PIPETX0CHARISK,
  output wire         PIPETX0COMPLIANCE,
  output wire  [31:0] PIPETX0DATA,
  output wire         PIPETX0DATAVALID,
  output wire         PIPETX0DEEMPH,
  output wire         PIPETX0ELECIDLE,
  output wire   [1:0] PIPETX0EQCONTROL,
  output wire   [5:0] PIPETX0EQDEEMPH,
  output wire   [3:0] PIPETX0EQPRESET,
  output wire   [2:0] PIPETX0MARGIN,
  output wire   [1:0] PIPETX0POWERDOWN,
  output wire   [1:0] PIPETX0RATE,
  output wire         PIPETX0RCVRDET,
  output wire         PIPETX0RESET,
  output wire         PIPETX0STARTBLOCK,
  output wire         PIPETX0SWING,
  output wire   [1:0] PIPETX0SYNCHEADER,
  output wire   [1:0] PIPETX1CHARISK,
  output wire         PIPETX1COMPLIANCE,
  output wire  [31:0] PIPETX1DATA,
  output wire         PIPETX1DATAVALID,
  output wire         PIPETX1DEEMPH,
  output wire         PIPETX1ELECIDLE,
  output wire   [1:0] PIPETX1EQCONTROL,
  output wire   [5:0] PIPETX1EQDEEMPH,
  output wire   [3:0] PIPETX1EQPRESET,
  output wire   [2:0] PIPETX1MARGIN,
  output wire   [1:0] PIPETX1POWERDOWN,
  output wire   [1:0] PIPETX1RATE,
  output wire         PIPETX1RCVRDET,
  output wire         PIPETX1RESET,
  output wire         PIPETX1STARTBLOCK,
  output wire         PIPETX1SWING,
  output wire   [1:0] PIPETX1SYNCHEADER,
  output wire   [1:0] PIPETX2CHARISK,
  output wire         PIPETX2COMPLIANCE,
  output wire  [31:0] PIPETX2DATA,
  output wire         PIPETX2DATAVALID,
  output wire         PIPETX2DEEMPH,
  output wire         PIPETX2ELECIDLE,
  output wire   [1:0] PIPETX2EQCONTROL,
  output wire   [5:0] PIPETX2EQDEEMPH,
  output wire   [3:0] PIPETX2EQPRESET,
  output wire   [2:0] PIPETX2MARGIN,
  output wire   [1:0] PIPETX2POWERDOWN,
  output wire   [1:0] PIPETX2RATE,
  output wire         PIPETX2RCVRDET,
  output wire         PIPETX2RESET,
  output wire         PIPETX2STARTBLOCK,
  output wire         PIPETX2SWING,
  output wire   [1:0] PIPETX2SYNCHEADER,
  output wire   [1:0] PIPETX3CHARISK,
  output wire         PIPETX3COMPLIANCE,
  output wire  [31:0] PIPETX3DATA,
  output wire         PIPETX3DATAVALID,
  output wire         PIPETX3DEEMPH,
  output wire         PIPETX3ELECIDLE,
  output wire   [1:0] PIPETX3EQCONTROL,
  output wire   [5:0] PIPETX3EQDEEMPH,
  output wire   [3:0] PIPETX3EQPRESET,
  output wire   [2:0] PIPETX3MARGIN,
  output wire   [1:0] PIPETX3POWERDOWN,
  output wire   [1:0] PIPETX3RATE,
  output wire         PIPETX3RCVRDET,
  output wire         PIPETX3RESET,
  output wire         PIPETX3STARTBLOCK,
  output wire         PIPETX3SWING,
  output wire   [1:0] PIPETX3SYNCHEADER,
  output wire   [1:0] PIPETX4CHARISK,
  output wire         PIPETX4COMPLIANCE,
  output wire  [31:0] PIPETX4DATA,
  output wire         PIPETX4DATAVALID,
  output wire         PIPETX4DEEMPH,
  output wire         PIPETX4ELECIDLE,
  output wire   [1:0] PIPETX4EQCONTROL,
  output wire   [5:0] PIPETX4EQDEEMPH,
  output wire   [3:0] PIPETX4EQPRESET,
  output wire   [2:0] PIPETX4MARGIN,
  output wire   [1:0] PIPETX4POWERDOWN,
  output wire   [1:0] PIPETX4RATE,
  output wire         PIPETX4RCVRDET,
  output wire         PIPETX4RESET,
  output wire         PIPETX4STARTBLOCK,
  output wire         PIPETX4SWING,
  output wire   [1:0] PIPETX4SYNCHEADER,
  output wire   [1:0] PIPETX5CHARISK,
  output wire         PIPETX5COMPLIANCE,
  output wire  [31:0] PIPETX5DATA,
  output wire         PIPETX5DATAVALID,
  output wire         PIPETX5DEEMPH,
  output wire         PIPETX5ELECIDLE,
  output wire   [1:0] PIPETX5EQCONTROL,
  output wire   [5:0] PIPETX5EQDEEMPH,
  output wire   [3:0] PIPETX5EQPRESET,
  output wire   [2:0] PIPETX5MARGIN,
  output wire   [1:0] PIPETX5POWERDOWN,
  output wire   [1:0] PIPETX5RATE,
  output wire         PIPETX5RCVRDET,
  output wire         PIPETX5RESET,
  output wire         PIPETX5STARTBLOCK,
  output wire         PIPETX5SWING,
  output wire   [1:0] PIPETX5SYNCHEADER,
  output wire   [1:0] PIPETX6CHARISK,
  output wire         PIPETX6COMPLIANCE,
  output wire  [31:0] PIPETX6DATA,
  output wire         PIPETX6DATAVALID,
  output wire         PIPETX6DEEMPH,
  output wire         PIPETX6ELECIDLE,
  output wire   [1:0] PIPETX6EQCONTROL,
  output wire   [5:0] PIPETX6EQDEEMPH,
  output wire   [3:0] PIPETX6EQPRESET,
  output wire   [2:0] PIPETX6MARGIN,
  output wire   [1:0] PIPETX6POWERDOWN,
  output wire   [1:0] PIPETX6RATE,
  output wire         PIPETX6RCVRDET,
  output wire         PIPETX6RESET,
  output wire         PIPETX6STARTBLOCK,
  output wire         PIPETX6SWING,
  output wire   [1:0] PIPETX6SYNCHEADER,
  output wire   [1:0] PIPETX7CHARISK,
  output wire         PIPETX7COMPLIANCE,
  output wire  [31:0] PIPETX7DATA,
  output wire         PIPETX7DATAVALID,
  output wire         PIPETX7DEEMPH,
  output wire         PIPETX7ELECIDLE,
  output wire   [1:0] PIPETX7EQCONTROL,
  output wire   [5:0] PIPETX7EQDEEMPH,
  output wire   [3:0] PIPETX7EQPRESET,
  output wire   [2:0] PIPETX7MARGIN,
  output wire   [1:0] PIPETX7POWERDOWN,
  output wire   [1:0] PIPETX7RATE,
  output wire         PIPETX7RCVRDET,
  output wire         PIPETX7RESET,
  output wire         PIPETX7STARTBLOCK,
  output wire         PIPETX7SWING,
  output wire   [1:0] PIPETX7SYNCHEADER,
  output wire         PLEQINPROGRESS,
  output wire   [1:0] PLEQPHASE,
  output wire   [3:0] SAXISCCTREADY,
  output wire   [3:0] SAXISRQTREADY,
  output wire  [31:0] SPAREOUT
  );

  wire        [143:0] MICOMPLETIONRAMREADDATA;
  wire        [143:0] MIREPLAYRAMREADDATA;
  wire        [143:0] MIREQUESTRAMREADDATA;
  wire          [9:0] MICOMPLETIONRAMREADADDRESSAL;
  wire          [9:0] MICOMPLETIONRAMREADADDRESSAU;
  wire          [9:0] MICOMPLETIONRAMREADADDRESSBL;
  wire          [9:0] MICOMPLETIONRAMREADADDRESSBU;
  wire          [3:0] MICOMPLETIONRAMREADENABLEL;
  wire          [3:0] MICOMPLETIONRAMREADENABLEU;
  wire          [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
  wire          [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
  wire          [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
  wire          [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
  wire         [71:0] MICOMPLETIONRAMWRITEDATAL;
  wire         [71:0] MICOMPLETIONRAMWRITEDATAU;
  wire          [3:0] MICOMPLETIONRAMWRITEENABLEL;
  wire          [3:0] MICOMPLETIONRAMWRITEENABLEU;
  wire          [8:0] MIREPLAYRAMADDRESS;
  wire          [1:0] MIREPLAYRAMREADENABLE;
  wire        [143:0] MIREPLAYRAMWRITEDATA;
  wire          [1:0] MIREPLAYRAMWRITEENABLE;
  wire          [8:0] MIREQUESTRAMREADADDRESSA;
  wire          [8:0] MIREQUESTRAMREADADDRESSB;
  wire          [3:0] MIREQUESTRAMREADENABLE;
  wire          [8:0] MIREQUESTRAMWRITEADDRESSA;
  wire          [8:0] MIREQUESTRAMWRITEADDRESSB;
  wire        [143:0] MIREQUESTRAMWRITEDATA;
  wire          [3:0] MIREQUESTRAMWRITEENABLE;
  wire        [143:0] micompletionramwritedata;
  wire         [15:0] mim_cpl_wdip;
  wire         [15:0] mim_rep_wdip;
  wire         [15:0] mim_req_wdip;
  wire         [15:0] mim_cpl_rdop;
  wire         [15:0] mim_rep_rdop;
  wire         [15:0] mim_req_rdop;
  wire        [127:0] mim_cpl_wdata;
  wire        [127:0] mim_rep_wdata;
  wire        [127:0] mim_req_wdata;
  wire        [127:0] mim_cpl_rdata;
  wire        [127:0] mim_rep_rdata;
  wire        [127:0] mim_req_rdata;

  wire  [255:0] MAXISCQTDATA_i;
  wire    [7:0] MAXISCQTKEEP_i;
  wire          MAXISCQTLAST_i;
  wire   [84:0] MAXISCQTUSER_i;
  wire          MAXISCQTVALID_i;


  wire [1:0]     PIPERX0SYNCHEADER_in_int = PIPERX0SYNCHEADER; 
  wire [1:0]     PIPERX1SYNCHEADER_in_int = PIPERX1SYNCHEADER; 
  wire [1:0]     PIPERX2SYNCHEADER_in_int = PIPERX2SYNCHEADER; 
  wire [1:0]     PIPERX3SYNCHEADER_in_int = PIPERX3SYNCHEADER; 
  wire [1:0]     PIPERX4SYNCHEADER_in_int = PIPERX4SYNCHEADER; 
  wire [1:0]     PIPERX5SYNCHEADER_in_int = PIPERX5SYNCHEADER; 
  wire [1:0]     PIPERX6SYNCHEADER_in_int = PIPERX6SYNCHEADER; 
  wire [1:0]     PIPERX7SYNCHEADER_in_int = PIPERX7SYNCHEADER; 
  wire           PIPERX0DATAVALID_in_int  = PIPERX0DATAVALID; 
  wire           PIPERX1DATAVALID_in_int  = PIPERX1DATAVALID; 
  wire           PIPERX2DATAVALID_in_int  = PIPERX2DATAVALID; 
  wire           PIPERX3DATAVALID_in_int  = PIPERX3DATAVALID; 
  wire           PIPERX4DATAVALID_in_int  = PIPERX4DATAVALID; 
  wire           PIPERX5DATAVALID_in_int  = PIPERX5DATAVALID; 
  wire           PIPERX6DATAVALID_in_int  = PIPERX6DATAVALID; 
  wire           PIPERX7DATAVALID_in_int  = PIPERX7DATAVALID; 
  wire [31:0]    PIPERX0DATA_in_int       = PIPERX0DATA; 
  wire [31:0]    PIPERX1DATA_in_int       = PIPERX1DATA; 
  wire [31:0]    PIPERX2DATA_in_int       = PIPERX2DATA; 
  wire [31:0]    PIPERX3DATA_in_int       = PIPERX3DATA; 
  wire [31:0]    PIPERX4DATA_in_int       = PIPERX4DATA; 
  wire [31:0]    PIPERX5DATA_in_int       = PIPERX5DATA; 
  wire [31:0]    PIPERX6DATA_in_int       = PIPERX6DATA; 
  wire [31:0]    PIPERX7DATA_in_int       = PIPERX7DATA; 
  wire           PIPERX0STARTBLOCK_in_int = PIPERX0STARTBLOCK; 
  wire           PIPERX1STARTBLOCK_in_int = PIPERX1STARTBLOCK; 
  wire           PIPERX2STARTBLOCK_in_int = PIPERX2STARTBLOCK; 
  wire           PIPERX3STARTBLOCK_in_int = PIPERX3STARTBLOCK; 
  wire           PIPERX4STARTBLOCK_in_int = PIPERX4STARTBLOCK; 
  wire           PIPERX5STARTBLOCK_in_int = PIPERX5STARTBLOCK; 
  wire           PIPERX6STARTBLOCK_in_int = PIPERX6STARTBLOCK; 
  wire           PIPERX7STARTBLOCK_in_int = PIPERX7STARTBLOCK; 
  wire [2:0]     PIPERX0STATUS_in_int     = PIPERX0STATUS; 
  wire [2:0]     PIPERX1STATUS_in_int     = PIPERX1STATUS; 
  wire [2:0]     PIPERX2STATUS_in_int     = PIPERX2STATUS; 
  wire [2:0]     PIPERX3STATUS_in_int     = PIPERX3STATUS; 
  wire [2:0]     PIPERX4STATUS_in_int     = PIPERX4STATUS; 
  wire [2:0]     PIPERX5STATUS_in_int     = PIPERX5STATUS; 
  wire [2:0]     PIPERX6STATUS_in_int     = PIPERX6STATUS; 
  wire [2:0]     PIPERX7STATUS_in_int     = PIPERX7STATUS; 

  assign MIREPLAYRAMREADDATA = {
    mim_rep_rdop[15], mim_rep_rdata[127:120], mim_rep_rdop[14], mim_rep_rdata[119:112],
    mim_rep_rdop[13], mim_rep_rdata[111:104], mim_rep_rdop[12], mim_rep_rdata[103:96],
    mim_rep_rdop[11], mim_rep_rdata[95:88], mim_rep_rdop[10], mim_rep_rdata[87:80],
    mim_rep_rdop[9], mim_rep_rdata[79:72], mim_rep_rdop[8], mim_rep_rdata[71:64],
    mim_rep_rdop[7], mim_rep_rdata[63:56], mim_rep_rdop[6], mim_rep_rdata[55:48],
    mim_rep_rdop[5], mim_rep_rdata[47:40], mim_rep_rdop[4], mim_rep_rdata[39:32],
    mim_rep_rdop[3], mim_rep_rdata[31:24], mim_rep_rdop[2], mim_rep_rdata[23:16],
    mim_rep_rdop[1], mim_rep_rdata[15:8], mim_rep_rdop[0], mim_rep_rdata[7:0]};

  assign mim_rep_wdip = {
    MIREPLAYRAMWRITEDATA[143], MIREPLAYRAMWRITEDATA[134],
    MIREPLAYRAMWRITEDATA[125], MIREPLAYRAMWRITEDATA[116],
    MIREPLAYRAMWRITEDATA[107], MIREPLAYRAMWRITEDATA[98],
    MIREPLAYRAMWRITEDATA[89], MIREPLAYRAMWRITEDATA[80],
    MIREPLAYRAMWRITEDATA[71], MIREPLAYRAMWRITEDATA[62],
    MIREPLAYRAMWRITEDATA[53], MIREPLAYRAMWRITEDATA[44],
    MIREPLAYRAMWRITEDATA[35], MIREPLAYRAMWRITEDATA[26],
    MIREPLAYRAMWRITEDATA[17], MIREPLAYRAMWRITEDATA[8]};

  assign mim_rep_wdata = {
    MIREPLAYRAMWRITEDATA[142:135], MIREPLAYRAMWRITEDATA[133:126],
    MIREPLAYRAMWRITEDATA[124:117], MIREPLAYRAMWRITEDATA[115:108],
    MIREPLAYRAMWRITEDATA[106:99], MIREPLAYRAMWRITEDATA[97:90],
    MIREPLAYRAMWRITEDATA[88:81], MIREPLAYRAMWRITEDATA[79:72],
    MIREPLAYRAMWRITEDATA[70:63], MIREPLAYRAMWRITEDATA[61:54],
    MIREPLAYRAMWRITEDATA[52:45], MIREPLAYRAMWRITEDATA[43:36],
    MIREPLAYRAMWRITEDATA[34:27], MIREPLAYRAMWRITEDATA[25:18],
    MIREPLAYRAMWRITEDATA[16:9], MIREPLAYRAMWRITEDATA[7:0]};

  assign MIREQUESTRAMREADDATA = {
    mim_req_rdop[15], mim_req_rdata[127:120], mim_req_rdop[14], mim_req_rdata[119:112],
    mim_req_rdop[13], mim_req_rdata[111:104], mim_req_rdop[12], mim_req_rdata[103:96],
    mim_req_rdop[11], mim_req_rdata[95:88], mim_req_rdop[10], mim_req_rdata[87:80],
    mim_req_rdop[9], mim_req_rdata[79:72], mim_req_rdop[8], mim_req_rdata[71:64],
    mim_req_rdop[7], mim_req_rdata[63:56], mim_req_rdop[6], mim_req_rdata[55:48],
    mim_req_rdop[5], mim_req_rdata[47:40], mim_req_rdop[4], mim_req_rdata[39:32],
    mim_req_rdop[3], mim_req_rdata[31:24], mim_req_rdop[2], mim_req_rdata[23:16],
    mim_req_rdop[1], mim_req_rdata[15:8], mim_req_rdop[0], mim_req_rdata[7:0]};

  assign mim_req_wdip = {
    MIREQUESTRAMWRITEDATA[143], MIREQUESTRAMWRITEDATA[134],
    MIREQUESTRAMWRITEDATA[125], MIREQUESTRAMWRITEDATA[116],
    MIREQUESTRAMWRITEDATA[107], MIREQUESTRAMWRITEDATA[98],
    MIREQUESTRAMWRITEDATA[89], MIREQUESTRAMWRITEDATA[80],
    MIREQUESTRAMWRITEDATA[71], MIREQUESTRAMWRITEDATA[62],
    MIREQUESTRAMWRITEDATA[53], MIREQUESTRAMWRITEDATA[44],
    MIREQUESTRAMWRITEDATA[35], MIREQUESTRAMWRITEDATA[26],
    MIREQUESTRAMWRITEDATA[17], MIREQUESTRAMWRITEDATA[8]};

  assign mim_req_wdata = {
    MIREQUESTRAMWRITEDATA[142:135], MIREQUESTRAMWRITEDATA[133:126],
    MIREQUESTRAMWRITEDATA[124:117], MIREQUESTRAMWRITEDATA[115:108],
    MIREQUESTRAMWRITEDATA[106:99], MIREQUESTRAMWRITEDATA[97:90],
    MIREQUESTRAMWRITEDATA[88:81], MIREQUESTRAMWRITEDATA[79:72],
    MIREQUESTRAMWRITEDATA[70:63], MIREQUESTRAMWRITEDATA[61:54],
    MIREQUESTRAMWRITEDATA[52:45], MIREQUESTRAMWRITEDATA[43:36],
    MIREQUESTRAMWRITEDATA[34:27], MIREQUESTRAMWRITEDATA[25:18],
    MIREQUESTRAMWRITEDATA[16:9], MIREQUESTRAMWRITEDATA[7:0]};

  assign MICOMPLETIONRAMREADDATA = {
    mim_cpl_rdop[15], mim_cpl_rdata[127:120], mim_cpl_rdop[14], mim_cpl_rdata[119:112],
    mim_cpl_rdop[13], mim_cpl_rdata[111:104], mim_cpl_rdop[12], mim_cpl_rdata[103:96],
    mim_cpl_rdop[11], mim_cpl_rdata[95:88], mim_cpl_rdop[10], mim_cpl_rdata[87:80],
    mim_cpl_rdop[9], mim_cpl_rdata[79:72], mim_cpl_rdop[8], mim_cpl_rdata[71:64],
    mim_cpl_rdop[7], mim_cpl_rdata[63:56], mim_cpl_rdop[6], mim_cpl_rdata[55:48],
    mim_cpl_rdop[5], mim_cpl_rdata[47:40], mim_cpl_rdop[4], mim_cpl_rdata[39:32],
    mim_cpl_rdop[3], mim_cpl_rdata[31:24], mim_cpl_rdop[2], mim_cpl_rdata[23:16],
    mim_cpl_rdop[1], mim_cpl_rdata[15:8], mim_cpl_rdop[0], mim_cpl_rdata[7:0]};

  assign micompletionramwritedata = {
    MICOMPLETIONRAMWRITEDATAU[71:0], MICOMPLETIONRAMWRITEDATAL[71:0]};

  assign mim_cpl_wdip = {
    micompletionramwritedata[143], micompletionramwritedata[134],
    micompletionramwritedata[125], micompletionramwritedata[116],
    micompletionramwritedata[107], micompletionramwritedata[98],
    micompletionramwritedata[89], micompletionramwritedata[80],
    micompletionramwritedata[71], micompletionramwritedata[62],
    micompletionramwritedata[53], micompletionramwritedata[44],
    micompletionramwritedata[35], micompletionramwritedata[26],
    micompletionramwritedata[17], micompletionramwritedata[8]};

  assign mim_cpl_wdata = {
    micompletionramwritedata[142:135], micompletionramwritedata[133:126],
    micompletionramwritedata[124:117], micompletionramwritedata[115:108],
    micompletionramwritedata[106:99], micompletionramwritedata[97:90],
    micompletionramwritedata[88:81], micompletionramwritedata[79:72],
    micompletionramwritedata[70:63], micompletionramwritedata[61:54],
    micompletionramwritedata[52:45], micompletionramwritedata[43:36],
    micompletionramwritedata[34:27], micompletionramwritedata[25:18],
    micompletionramwritedata[16:9], micompletionramwritedata[7:0]};

  xdma_x8gen3_pcie3_ip_bram #(
    .TCQ (TCQ),
    .COMPLETION_SPACE (COMPLETION_SPACE))
  bram_inst (
    .clk_i (CORECLK),
    .reset_i (1'b1),
    .mi_rep_addr_i (MIREPLAYRAMADDRESS),
    .mi_rep_wdata_i (mim_rep_wdata[127:0]),
    .mi_rep_wdip_i (mim_rep_wdip[15:0]),
    .mi_rep_wen0_i (MIREPLAYRAMWRITEENABLE[0]),
    .mi_rep_wen1_i (MIREPLAYRAMWRITEENABLE[1]),
    .mi_rep_rdata_o (mim_rep_rdata[127:0]),
    .mi_rep_rdop_o (mim_rep_rdop[15:0]),
    .mi_rep_rden0_i (MIREPLAYRAMREADENABLE[0]),
    .mi_rep_rden1_i (MIREPLAYRAMREADENABLE[1]),
    .mi_req_waddr0_i (MIREQUESTRAMWRITEADDRESSA),
    .mi_req_waddr1_i (MIREQUESTRAMWRITEADDRESSB),
    .mi_req_wdata_i (mim_req_wdata[127:0]),
    .mi_req_wdip_i (mim_req_wdip[15:0]),
    .mi_req_wen0_i (MIREQUESTRAMWRITEENABLE[0]),
    .mi_req_wen1_i (MIREQUESTRAMWRITEENABLE[1]),
    .mi_req_wen2_i (MIREQUESTRAMWRITEENABLE[2]),
    .mi_req_wen3_i (MIREQUESTRAMWRITEENABLE[3]),
    .mi_req_raddr0_i (MIREQUESTRAMREADADDRESSA),
    .mi_req_raddr1_i (MIREQUESTRAMREADADDRESSB),
    .mi_req_rdata_o (mim_req_rdata[127:0]),
    .mi_req_rdop_o (mim_req_rdop[15:0]),
    .mi_req_ren0_i (MIREQUESTRAMREADENABLE[0]),
    .mi_req_ren1_i (MIREQUESTRAMREADENABLE[1]),
    .mi_req_ren2_i (MIREQUESTRAMREADENABLE[2]),
    .mi_req_ren3_i (MIREQUESTRAMREADENABLE[3]),
    .mi_cpl_waddr0_i (MICOMPLETIONRAMWRITEADDRESSAL),
    .mi_cpl_waddr1_i (MICOMPLETIONRAMWRITEADDRESSBL),
    .mi_cpl_waddr2_i (MICOMPLETIONRAMWRITEADDRESSAU),
    .mi_cpl_waddr3_i (MICOMPLETIONRAMWRITEADDRESSBU),
    .mi_cpl_wdata_i (mim_cpl_wdata[127:0]),
    .mi_cpl_wdip_i (mim_cpl_wdip[15:0]),
    .mi_cpl_wen0_i (MICOMPLETIONRAMWRITEENABLEL[0]),
    .mi_cpl_wen1_i (MICOMPLETIONRAMWRITEENABLEL[1]),
    .mi_cpl_wen2_i (MICOMPLETIONRAMWRITEENABLEL[2]),
    .mi_cpl_wen3_i (MICOMPLETIONRAMWRITEENABLEL[3]),
    .mi_cpl_wen4_i (MICOMPLETIONRAMWRITEENABLEU[0]),
    .mi_cpl_wen5_i (MICOMPLETIONRAMWRITEENABLEU[1]),
    .mi_cpl_wen6_i (MICOMPLETIONRAMWRITEENABLEU[2]),
    .mi_cpl_wen7_i (MICOMPLETIONRAMWRITEENABLEU[3]),
    .mi_cpl_raddr0_i (MICOMPLETIONRAMREADADDRESSAL),
    .mi_cpl_raddr1_i (MICOMPLETIONRAMREADADDRESSBL),
    .mi_cpl_raddr2_i (MICOMPLETIONRAMREADADDRESSAU),
    .mi_cpl_raddr3_i (MICOMPLETIONRAMREADADDRESSBU),
    .mi_cpl_rdata_o (mim_cpl_rdata[127:0]),
    .mi_cpl_rdop_o (mim_cpl_rdop[15:0]),
    .mi_cpl_ren0_i (MICOMPLETIONRAMREADENABLEL[0]),
    .mi_cpl_ren1_i (MICOMPLETIONRAMREADENABLEL[1]),
    .mi_cpl_ren2_i (MICOMPLETIONRAMREADENABLEL[2]),
    .mi_cpl_ren3_i (MICOMPLETIONRAMREADENABLEL[3]),
    .mi_cpl_ren4_i (MICOMPLETIONRAMREADENABLEU[0]),
    .mi_cpl_ren5_i (MICOMPLETIONRAMREADENABLEU[1]),
    .mi_cpl_ren6_i (MICOMPLETIONRAMREADENABLEU[2]),
    .mi_cpl_ren7_i (MICOMPLETIONRAMREADENABLEU[3])
  );

  PCIE_3_1 #(
    .ARI_CAP_ENABLE (ARI_CAP_ENABLE),
    .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE),
    .AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK),
    .AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE),
    .AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG),
    .AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE),
    .AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC),
    .AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE),
    .AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE),
    .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE),
    .AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK),
    .AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH),
    .CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500),
    .CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ),
    .DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE (DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE),
    .DEBUG_PL_DISABLE_EI_INFER_IN_L0 (DEBUG_PL_DISABLE_EI_INFER_IN_L0),
    .DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS (DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS),
    .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
    .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
    .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
    .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
    .LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER),
    .LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE),
    .LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER),
    .LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE),
    .LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER),
    .LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE),
    .LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER),
    .LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE),
    .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
    .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
    .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
    .LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL),
    .LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE),
    .LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE),
    .MCAP_CAP_NEXTPTR (MCAP_CAP_NEXTPTR),
    .MCAP_CONFIGURE_OVERRIDE (MCAP_CONFIGURE_OVERRIDE),
    .MCAP_ENABLE (MCAP_ENABLE),
    .MCAP_EOS_DESIGN_SWITCH (MCAP_EOS_DESIGN_SWITCH),
    .MCAP_FPGA_BITSTREAM_VERSION (MCAP_FPGA_BITSTREAM_VERSION),
    .MCAP_GATE_IO_ENABLE_DESIGN_SWITCH (MCAP_GATE_IO_ENABLE_DESIGN_SWITCH),
    .MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH (MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH),
    .MCAP_INPUT_GATE_DESIGN_SWITCH (MCAP_INPUT_GATE_DESIGN_SWITCH),
    .MCAP_INTERRUPT_ON_MCAP_EOS (MCAP_INTERRUPT_ON_MCAP_EOS),
    .MCAP_INTERRUPT_ON_MCAP_ERROR (MCAP_INTERRUPT_ON_MCAP_ERROR),
    .MCAP_VSEC_ID (MCAP_VSEC_ID),
    .MCAP_VSEC_LEN (MCAP_VSEC_LEN),
    .MCAP_VSEC_REV (MCAP_VSEC_REV),
    .PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE),
    .PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR),
    .PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC),
    .PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR),
    .PF0_ARI_CAP_VER (PF0_ARI_CAP_VER),
    .PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE),
    .PF0_BAR0_CONTROL (PF0_BAR0_CONTROL),
    .PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE),
    .PF0_BAR1_CONTROL (PF0_BAR1_CONTROL),
    .PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE),
    .PF0_BAR2_CONTROL (PF0_BAR2_CONTROL),
    .PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE),
    .PF0_BAR3_CONTROL (PF0_BAR3_CONTROL),
    .PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE),
    .PF0_BAR4_CONTROL (PF0_BAR4_CONTROL),
    .PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE),
    .PF0_BAR5_CONTROL (PF0_BAR5_CONTROL),
    .PF0_BIST_REGISTER (PF0_BIST_REGISTER),
    .PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER),
    .PF0_CLASS_CODE (PF0_CLASS_CODE),
    .PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY),
    .PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY),
    .PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED),
    .PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
    .PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF0_DEV_CAP2_ARI_FORWARD_ENABLE (PF0_DEV_CAP2_ARI_FORWARD_ENABLE),
    .PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE),
    .PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT),
    .PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT),
    .PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT),
    .PF0_DEVICE_ID (PF0_DEVICE_ID),
    .PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR),
    .PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL),
    .PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF0_DPA_CAP_VER (PF0_DPA_CAP_VER),
    .PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR),
    .PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE),
    .PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE),
    .PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE),
    .PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN),
    .PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2),
    .PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2),
    .PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3),
    .PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG),
    .PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT),
    .PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT),
    .PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR),
    .PF0_LTR_CAP_VER (PF0_LTR_CAP_VER),
    .PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP),
    .PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR),
    .PF0_MSI_CAP_PERVECMASKCAP (PF0_MSI_CAP_PERVECMASKCAP),
    .PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR),
    .PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR),
    .PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET),
    .PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR),
    .PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET),
    .PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE),
    .PF0_PB_CAP_DATA_REG_D0 (PF0_PB_CAP_DATA_REG_D0),
    .PF0_PB_CAP_DATA_REG_D0_SUSTAINED (PF0_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF0_PB_CAP_DATA_REG_D1 (PF0_PB_CAP_DATA_REG_D1),
    .PF0_PB_CAP_DATA_REG_D3HOT (PF0_PB_CAP_DATA_REG_D3HOT),
    .PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR),
    .PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED),
    .PF0_PB_CAP_VER (PF0_PB_CAP_VER),
    .PF0_PM_CAP_ID (PF0_PM_CAP_ID),
    .PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR),
    .PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0),
    .PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1),
    .PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT),
    .PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE),
    .PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID),
    .PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET),
    .PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE),
    .PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR),
    .PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0),
    .PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1),
    .PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2),
    .PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER),
    .PF0_RBAR_CONTROL_INDEX0 (PF0_RBAR_CONTROL_INDEX0),
    .PF0_RBAR_CONTROL_INDEX1 (PF0_RBAR_CONTROL_INDEX1),
    .PF0_RBAR_CONTROL_INDEX2 (PF0_RBAR_CONTROL_INDEX2),
    .PF0_RBAR_CONTROL_SIZE0 (PF0_RBAR_CONTROL_SIZE0),
    .PF0_RBAR_CONTROL_SIZE1 (PF0_RBAR_CONTROL_SIZE1),
    .PF0_RBAR_CONTROL_SIZE2 (PF0_RBAR_CONTROL_SIZE2),
    .PF0_RBAR_NUM (PF0_RBAR_NUM),
    .PF0_REVISION_ID (PF0_REVISION_ID),
    .PF0_SECONDARY_PCIE_CAP_NEXTPTR (PF0_SECONDARY_PCIE_CAP_NEXTPTR),
    .PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE),
    .PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL),
    .PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE),
    .PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL),
    .PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE),
    .PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL),
    .PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE),
    .PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL),
    .PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE),
    .PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL),
    .PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE),
    .PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL),
    .PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF),
    .PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR),
    .PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF),
    .PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER),
    .PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET),
    .PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK),
    .PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID),
    .PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID),
    .PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE),
    .PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE),
    .PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR),
    .PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL),
    .PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC),
    .PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE),
    .PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER),
    .PF0_VC_CAP_ENABLE (PF0_VC_CAP_ENABLE),
    .PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR),
    .PF0_VC_CAP_VER (PF0_VC_CAP_VER),
    .PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE),
    .PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR),
    .PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC),
    .PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR),
    .PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE),
    .PF1_BAR0_CONTROL (PF1_BAR0_CONTROL),
    .PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE),
    .PF1_BAR1_CONTROL (PF1_BAR1_CONTROL),
    .PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE),
    .PF1_BAR2_CONTROL (PF1_BAR2_CONTROL),
    .PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE),
    .PF1_BAR3_CONTROL (PF1_BAR3_CONTROL),
    .PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE),
    .PF1_BAR4_CONTROL (PF1_BAR4_CONTROL),
    .PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE),
    .PF1_BAR5_CONTROL (PF1_BAR5_CONTROL),
    .PF1_BIST_REGISTER (PF1_BIST_REGISTER),
    .PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER),
    .PF1_CLASS_CODE (PF1_CLASS_CODE),
    .PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF1_DEVICE_ID (PF1_DEVICE_ID),
    .PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR),
    .PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL),
    .PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF1_DPA_CAP_VER (PF1_DPA_CAP_VER),
    .PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR),
    .PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE),
    .PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE),
    .PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE),
    .PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN),
    .PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP),
    .PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR),
    .PF1_MSI_CAP_PERVECMASKCAP (PF1_MSI_CAP_PERVECMASKCAP),
    .PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR),
    .PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR),
    .PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET),
    .PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR),
    .PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET),
    .PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE),
    .PF1_PB_CAP_DATA_REG_D0 (PF1_PB_CAP_DATA_REG_D0),
    .PF1_PB_CAP_DATA_REG_D0_SUSTAINED (PF1_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF1_PB_CAP_DATA_REG_D1 (PF1_PB_CAP_DATA_REG_D1),
    .PF1_PB_CAP_DATA_REG_D3HOT (PF1_PB_CAP_DATA_REG_D3HOT),
    .PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR),
    .PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED),
    .PF1_PB_CAP_VER (PF1_PB_CAP_VER),
    .PF1_PM_CAP_ID (PF1_PM_CAP_ID),
    .PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR),
    .PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID),
    .PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE),
    .PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR),
    .PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0),
    .PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1),
    .PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2),
    .PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER),
    .PF1_RBAR_CONTROL_INDEX0 (PF1_RBAR_CONTROL_INDEX0),
    .PF1_RBAR_CONTROL_INDEX1 (PF1_RBAR_CONTROL_INDEX1),
    .PF1_RBAR_CONTROL_INDEX2 (PF1_RBAR_CONTROL_INDEX2),
    .PF1_RBAR_CONTROL_SIZE0 (PF1_RBAR_CONTROL_SIZE0),
    .PF1_RBAR_CONTROL_SIZE1 (PF1_RBAR_CONTROL_SIZE1),
    .PF1_RBAR_CONTROL_SIZE2 (PF1_RBAR_CONTROL_SIZE2),
    .PF1_RBAR_NUM (PF1_RBAR_NUM),
    .PF1_REVISION_ID (PF1_REVISION_ID),
    .PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE),
    .PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL),
    .PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE),
    .PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL),
    .PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE),
    .PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL),
    .PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE),
    .PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL),
    .PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE),
    .PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL),
    .PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE),
    .PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL),
    .PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF),
    .PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR),
    .PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF),
    .PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER),
    .PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET),
    .PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK),
    .PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID),
    .PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID),
    .PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE),
    .PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE),
    .PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR),
    .PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL),
    .PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC),
    .PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE),
    .PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER),
    .PF2_AER_CAP_ECRC_CHECK_CAPABLE (PF2_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF2_AER_CAP_ECRC_GEN_CAPABLE (PF2_AER_CAP_ECRC_GEN_CAPABLE),
    .PF2_AER_CAP_NEXTPTR (PF2_AER_CAP_NEXTPTR),
    .PF2_ARI_CAP_NEXT_FUNC (PF2_ARI_CAP_NEXT_FUNC),
    .PF2_ARI_CAP_NEXTPTR (PF2_ARI_CAP_NEXTPTR),
    .PF2_BAR0_APERTURE_SIZE (PF2_BAR0_APERTURE_SIZE),
    .PF2_BAR0_CONTROL (PF2_BAR0_CONTROL),
    .PF2_BAR1_APERTURE_SIZE (PF2_BAR1_APERTURE_SIZE),
    .PF2_BAR1_CONTROL (PF2_BAR1_CONTROL),
    .PF2_BAR2_APERTURE_SIZE (PF2_BAR2_APERTURE_SIZE),
    .PF2_BAR2_CONTROL (PF2_BAR2_CONTROL),
    .PF2_BAR3_APERTURE_SIZE (PF2_BAR3_APERTURE_SIZE),
    .PF2_BAR3_CONTROL (PF2_BAR3_CONTROL),
    .PF2_BAR4_APERTURE_SIZE (PF2_BAR4_APERTURE_SIZE),
    .PF2_BAR4_CONTROL (PF2_BAR4_CONTROL),
    .PF2_BAR5_APERTURE_SIZE (PF2_BAR5_APERTURE_SIZE),
    .PF2_BAR5_CONTROL (PF2_BAR5_CONTROL),
    .PF2_BIST_REGISTER (PF2_BIST_REGISTER),
    .PF2_CAPABILITY_POINTER (PF2_CAPABILITY_POINTER),
    .PF2_CLASS_CODE (PF2_CLASS_CODE),
    .PF2_DEV_CAP_MAX_PAYLOAD_SIZE (PF2_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF2_DEVICE_ID (PF2_DEVICE_ID),
    .PF2_DPA_CAP_NEXTPTR (PF2_DPA_CAP_NEXTPTR),
    .PF2_DPA_CAP_SUB_STATE_CONTROL (PF2_DPA_CAP_SUB_STATE_CONTROL),
    .PF2_DPA_CAP_SUB_STATE_CONTROL_EN (PF2_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF2_DPA_CAP_VER (PF2_DPA_CAP_VER),
    .PF2_DSN_CAP_NEXTPTR (PF2_DSN_CAP_NEXTPTR),
    .PF2_EXPANSION_ROM_APERTURE_SIZE (PF2_EXPANSION_ROM_APERTURE_SIZE),
    .PF2_EXPANSION_ROM_ENABLE (PF2_EXPANSION_ROM_ENABLE),
    .PF2_INTERRUPT_LINE (PF2_INTERRUPT_LINE),
    .PF2_INTERRUPT_PIN (PF2_INTERRUPT_PIN),
    .PF2_MSI_CAP_MULTIMSGCAP (PF2_MSI_CAP_MULTIMSGCAP),
    .PF2_MSI_CAP_NEXTPTR (PF2_MSI_CAP_NEXTPTR),
    .PF2_MSI_CAP_PERVECMASKCAP (PF2_MSI_CAP_PERVECMASKCAP),
    .PF2_MSIX_CAP_NEXTPTR (PF2_MSIX_CAP_NEXTPTR),
    .PF2_MSIX_CAP_PBA_BIR (PF2_MSIX_CAP_PBA_BIR),
    .PF2_MSIX_CAP_PBA_OFFSET (PF2_MSIX_CAP_PBA_OFFSET),
    .PF2_MSIX_CAP_TABLE_BIR (PF2_MSIX_CAP_TABLE_BIR),
    .PF2_MSIX_CAP_TABLE_OFFSET (PF2_MSIX_CAP_TABLE_OFFSET),
    .PF2_MSIX_CAP_TABLE_SIZE (PF2_MSIX_CAP_TABLE_SIZE),
    .PF2_PB_CAP_DATA_REG_D0 (PF2_PB_CAP_DATA_REG_D0),
    .PF2_PB_CAP_DATA_REG_D0_SUSTAINED (PF2_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF2_PB_CAP_DATA_REG_D1 (PF2_PB_CAP_DATA_REG_D1),
    .PF2_PB_CAP_DATA_REG_D3HOT (PF2_PB_CAP_DATA_REG_D3HOT),
    .PF2_PB_CAP_NEXTPTR (PF2_PB_CAP_NEXTPTR),
    .PF2_PB_CAP_SYSTEM_ALLOCATED (PF2_PB_CAP_SYSTEM_ALLOCATED),
    .PF2_PB_CAP_VER (PF2_PB_CAP_VER),
    .PF2_PM_CAP_ID (PF2_PM_CAP_ID),
    .PF2_PM_CAP_NEXTPTR (PF2_PM_CAP_NEXTPTR),
    .PF2_PM_CAP_VER_ID (PF2_PM_CAP_VER_ID),
    .PF2_RBAR_CAP_ENABLE (PF2_RBAR_CAP_ENABLE),
    .PF2_RBAR_CAP_NEXTPTR (PF2_RBAR_CAP_NEXTPTR),
    .PF2_RBAR_CAP_SIZE0 (PF2_RBAR_CAP_SIZE0),
    .PF2_RBAR_CAP_SIZE1 (PF2_RBAR_CAP_SIZE1),
    .PF2_RBAR_CAP_SIZE2 (PF2_RBAR_CAP_SIZE2),
    .PF2_RBAR_CAP_VER (PF2_RBAR_CAP_VER),
    .PF2_RBAR_CONTROL_INDEX0 (PF2_RBAR_CONTROL_INDEX0),
    .PF2_RBAR_CONTROL_INDEX1 (PF2_RBAR_CONTROL_INDEX1),
    .PF2_RBAR_CONTROL_INDEX2 (PF2_RBAR_CONTROL_INDEX2),
    .PF2_RBAR_CONTROL_SIZE0 (PF2_RBAR_CONTROL_SIZE0),
    .PF2_RBAR_CONTROL_SIZE1 (PF2_RBAR_CONTROL_SIZE1),
    .PF2_RBAR_CONTROL_SIZE2 (PF2_RBAR_CONTROL_SIZE2),
    .PF2_RBAR_NUM (PF2_RBAR_NUM),
    .PF2_REVISION_ID (PF2_REVISION_ID),
    .PF2_SRIOV_BAR0_APERTURE_SIZE (PF2_SRIOV_BAR0_APERTURE_SIZE),
    .PF2_SRIOV_BAR0_CONTROL (PF2_SRIOV_BAR0_CONTROL),
    .PF2_SRIOV_BAR1_APERTURE_SIZE (PF2_SRIOV_BAR1_APERTURE_SIZE),
    .PF2_SRIOV_BAR1_CONTROL (PF2_SRIOV_BAR1_CONTROL),
    .PF2_SRIOV_BAR2_APERTURE_SIZE (PF2_SRIOV_BAR2_APERTURE_SIZE),
    .PF2_SRIOV_BAR2_CONTROL (PF2_SRIOV_BAR2_CONTROL),
    .PF2_SRIOV_BAR3_APERTURE_SIZE (PF2_SRIOV_BAR3_APERTURE_SIZE),
    .PF2_SRIOV_BAR3_CONTROL (PF2_SRIOV_BAR3_CONTROL),
    .PF2_SRIOV_BAR4_APERTURE_SIZE (PF2_SRIOV_BAR4_APERTURE_SIZE),
    .PF2_SRIOV_BAR4_CONTROL (PF2_SRIOV_BAR4_CONTROL),
    .PF2_SRIOV_BAR5_APERTURE_SIZE (PF2_SRIOV_BAR5_APERTURE_SIZE),
    .PF2_SRIOV_BAR5_CONTROL (PF2_SRIOV_BAR5_CONTROL),
    .PF2_SRIOV_CAP_INITIAL_VF (PF2_SRIOV_CAP_INITIAL_VF),
    .PF2_SRIOV_CAP_NEXTPTR (PF2_SRIOV_CAP_NEXTPTR),
    .PF2_SRIOV_CAP_TOTAL_VF (PF2_SRIOV_CAP_TOTAL_VF),
    .PF2_SRIOV_CAP_VER (PF2_SRIOV_CAP_VER),
    .PF2_SRIOV_FIRST_VF_OFFSET (PF2_SRIOV_FIRST_VF_OFFSET),
    .PF2_SRIOV_FUNC_DEP_LINK (PF2_SRIOV_FUNC_DEP_LINK),
    .PF2_SRIOV_SUPPORTED_PAGE_SIZE (PF2_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF2_SRIOV_VF_DEVICE_ID (PF2_SRIOV_VF_DEVICE_ID),
    .PF2_SUBSYSTEM_ID (PF2_SUBSYSTEM_ID),
    .PF2_TPHR_CAP_DEV_SPECIFIC_MODE (PF2_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF2_TPHR_CAP_ENABLE (PF2_TPHR_CAP_ENABLE),
    .PF2_TPHR_CAP_INT_VEC_MODE (PF2_TPHR_CAP_INT_VEC_MODE),
    .PF2_TPHR_CAP_NEXTPTR (PF2_TPHR_CAP_NEXTPTR),
    .PF2_TPHR_CAP_ST_MODE_SEL (PF2_TPHR_CAP_ST_MODE_SEL),
    .PF2_TPHR_CAP_ST_TABLE_LOC (PF2_TPHR_CAP_ST_TABLE_LOC),
    .PF2_TPHR_CAP_ST_TABLE_SIZE (PF2_TPHR_CAP_ST_TABLE_SIZE),
    .PF2_TPHR_CAP_VER (PF2_TPHR_CAP_VER),
    .PF3_AER_CAP_ECRC_CHECK_CAPABLE (PF3_AER_CAP_ECRC_CHECK_CAPABLE),
    .PF3_AER_CAP_ECRC_GEN_CAPABLE (PF3_AER_CAP_ECRC_GEN_CAPABLE),
    .PF3_AER_CAP_NEXTPTR (PF3_AER_CAP_NEXTPTR),
    .PF3_ARI_CAP_NEXT_FUNC (PF3_ARI_CAP_NEXT_FUNC),
    .PF3_ARI_CAP_NEXTPTR (PF3_ARI_CAP_NEXTPTR),
    .PF3_BAR0_APERTURE_SIZE (PF3_BAR0_APERTURE_SIZE),
    .PF3_BAR0_CONTROL (PF3_BAR0_CONTROL),
    .PF3_BAR1_APERTURE_SIZE (PF3_BAR1_APERTURE_SIZE),
    .PF3_BAR1_CONTROL (PF3_BAR1_CONTROL),
    .PF3_BAR2_APERTURE_SIZE (PF3_BAR2_APERTURE_SIZE),
    .PF3_BAR2_CONTROL (PF3_BAR2_CONTROL),
    .PF3_BAR3_APERTURE_SIZE (PF3_BAR3_APERTURE_SIZE),
    .PF3_BAR3_CONTROL (PF3_BAR3_CONTROL),
    .PF3_BAR4_APERTURE_SIZE (PF3_BAR4_APERTURE_SIZE),
    .PF3_BAR4_CONTROL (PF3_BAR4_CONTROL),
    .PF3_BAR5_APERTURE_SIZE (PF3_BAR5_APERTURE_SIZE),
    .PF3_BAR5_CONTROL (PF3_BAR5_CONTROL),
    .PF3_BIST_REGISTER (PF3_BIST_REGISTER),
    .PF3_CAPABILITY_POINTER (PF3_CAPABILITY_POINTER),
    .PF3_CLASS_CODE (PF3_CLASS_CODE),
    .PF3_DEV_CAP_MAX_PAYLOAD_SIZE (PF3_DEV_CAP_MAX_PAYLOAD_SIZE),
    .PF3_DEVICE_ID (PF3_DEVICE_ID),
    .PF3_DPA_CAP_NEXTPTR (PF3_DPA_CAP_NEXTPTR),
    .PF3_DPA_CAP_SUB_STATE_CONTROL (PF3_DPA_CAP_SUB_STATE_CONTROL),
    .PF3_DPA_CAP_SUB_STATE_CONTROL_EN (PF3_DPA_CAP_SUB_STATE_CONTROL_EN),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
    .PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
    .PF3_DPA_CAP_VER (PF3_DPA_CAP_VER),
    .PF3_DSN_CAP_NEXTPTR (PF3_DSN_CAP_NEXTPTR),
    .PF3_EXPANSION_ROM_APERTURE_SIZE (PF3_EXPANSION_ROM_APERTURE_SIZE),
    .PF3_EXPANSION_ROM_ENABLE (PF3_EXPANSION_ROM_ENABLE),
    .PF3_INTERRUPT_LINE (PF3_INTERRUPT_LINE),
    .PF3_INTERRUPT_PIN (PF3_INTERRUPT_PIN),
    .PF3_MSI_CAP_MULTIMSGCAP (PF3_MSI_CAP_MULTIMSGCAP),
    .PF3_MSI_CAP_NEXTPTR (PF3_MSI_CAP_NEXTPTR),
    .PF3_MSI_CAP_PERVECMASKCAP (PF3_MSI_CAP_PERVECMASKCAP),
    .PF3_MSIX_CAP_NEXTPTR (PF3_MSIX_CAP_NEXTPTR),
    .PF3_MSIX_CAP_PBA_BIR (PF3_MSIX_CAP_PBA_BIR),
    .PF3_MSIX_CAP_PBA_OFFSET (PF3_MSIX_CAP_PBA_OFFSET),
    .PF3_MSIX_CAP_TABLE_BIR (PF3_MSIX_CAP_TABLE_BIR),
    .PF3_MSIX_CAP_TABLE_OFFSET (PF3_MSIX_CAP_TABLE_OFFSET),
    .PF3_MSIX_CAP_TABLE_SIZE (PF3_MSIX_CAP_TABLE_SIZE),
    .PF3_PB_CAP_DATA_REG_D0 (PF3_PB_CAP_DATA_REG_D0),
    .PF3_PB_CAP_DATA_REG_D0_SUSTAINED (PF3_PB_CAP_DATA_REG_D0_SUSTAINED),
    .PF3_PB_CAP_DATA_REG_D1 (PF3_PB_CAP_DATA_REG_D1),
    .PF3_PB_CAP_DATA_REG_D3HOT (PF3_PB_CAP_DATA_REG_D3HOT),
    .PF3_PB_CAP_NEXTPTR (PF3_PB_CAP_NEXTPTR),
    .PF3_PB_CAP_SYSTEM_ALLOCATED (PF3_PB_CAP_SYSTEM_ALLOCATED),
    .PF3_PB_CAP_VER (PF3_PB_CAP_VER),
    .PF3_PM_CAP_ID (PF3_PM_CAP_ID),
    .PF3_PM_CAP_NEXTPTR (PF3_PM_CAP_NEXTPTR),
    .PF3_PM_CAP_VER_ID (PF3_PM_CAP_VER_ID),
    .PF3_RBAR_CAP_ENABLE (PF3_RBAR_CAP_ENABLE),
    .PF3_RBAR_CAP_NEXTPTR (PF3_RBAR_CAP_NEXTPTR),
    .PF3_RBAR_CAP_SIZE0 (PF3_RBAR_CAP_SIZE0),
    .PF3_RBAR_CAP_SIZE1 (PF3_RBAR_CAP_SIZE1),
    .PF3_RBAR_CAP_SIZE2 (PF3_RBAR_CAP_SIZE2),
    .PF3_RBAR_CAP_VER (PF3_RBAR_CAP_VER),
    .PF3_RBAR_CONTROL_INDEX0 (PF3_RBAR_CONTROL_INDEX0),
    .PF3_RBAR_CONTROL_INDEX1 (PF3_RBAR_CONTROL_INDEX1),
    .PF3_RBAR_CONTROL_INDEX2 (PF3_RBAR_CONTROL_INDEX2),
    .PF3_RBAR_CONTROL_SIZE0 (PF3_RBAR_CONTROL_SIZE0),
    .PF3_RBAR_CONTROL_SIZE1 (PF3_RBAR_CONTROL_SIZE1),
    .PF3_RBAR_CONTROL_SIZE2 (PF3_RBAR_CONTROL_SIZE2),
    .PF3_RBAR_NUM (PF3_RBAR_NUM),
    .PF3_REVISION_ID (PF3_REVISION_ID),
    .PF3_SRIOV_BAR0_APERTURE_SIZE (PF3_SRIOV_BAR0_APERTURE_SIZE),
    .PF3_SRIOV_BAR0_CONTROL (PF3_SRIOV_BAR0_CONTROL),
    .PF3_SRIOV_BAR1_APERTURE_SIZE (PF3_SRIOV_BAR1_APERTURE_SIZE),
    .PF3_SRIOV_BAR1_CONTROL (PF3_SRIOV_BAR1_CONTROL),
    .PF3_SRIOV_BAR2_APERTURE_SIZE (PF3_SRIOV_BAR2_APERTURE_SIZE),
    .PF3_SRIOV_BAR2_CONTROL (PF3_SRIOV_BAR2_CONTROL),
    .PF3_SRIOV_BAR3_APERTURE_SIZE (PF3_SRIOV_BAR3_APERTURE_SIZE),
    .PF3_SRIOV_BAR3_CONTROL (PF3_SRIOV_BAR3_CONTROL),
    .PF3_SRIOV_BAR4_APERTURE_SIZE (PF3_SRIOV_BAR4_APERTURE_SIZE),
    .PF3_SRIOV_BAR4_CONTROL (PF3_SRIOV_BAR4_CONTROL),
    .PF3_SRIOV_BAR5_APERTURE_SIZE (PF3_SRIOV_BAR5_APERTURE_SIZE),
    .PF3_SRIOV_BAR5_CONTROL (PF3_SRIOV_BAR5_CONTROL),
    .PF3_SRIOV_CAP_INITIAL_VF (PF3_SRIOV_CAP_INITIAL_VF),
    .PF3_SRIOV_CAP_NEXTPTR (PF3_SRIOV_CAP_NEXTPTR),
    .PF3_SRIOV_CAP_TOTAL_VF (PF3_SRIOV_CAP_TOTAL_VF),
    .PF3_SRIOV_CAP_VER (PF3_SRIOV_CAP_VER),
    .PF3_SRIOV_FIRST_VF_OFFSET (PF3_SRIOV_FIRST_VF_OFFSET),
    .PF3_SRIOV_FUNC_DEP_LINK (PF3_SRIOV_FUNC_DEP_LINK),
    .PF3_SRIOV_SUPPORTED_PAGE_SIZE (PF3_SRIOV_SUPPORTED_PAGE_SIZE),
    .PF3_SRIOV_VF_DEVICE_ID (PF3_SRIOV_VF_DEVICE_ID),
    .PF3_SUBSYSTEM_ID (PF3_SUBSYSTEM_ID),
    .PF3_TPHR_CAP_DEV_SPECIFIC_MODE (PF3_TPHR_CAP_DEV_SPECIFIC_MODE),
    .PF3_TPHR_CAP_ENABLE (PF3_TPHR_CAP_ENABLE),
    .PF3_TPHR_CAP_INT_VEC_MODE (PF3_TPHR_CAP_INT_VEC_MODE),
    .PF3_TPHR_CAP_NEXTPTR (PF3_TPHR_CAP_NEXTPTR),
    .PF3_TPHR_CAP_ST_MODE_SEL (PF3_TPHR_CAP_ST_MODE_SEL),
    .PF3_TPHR_CAP_ST_TABLE_LOC (PF3_TPHR_CAP_ST_TABLE_LOC),
    .PF3_TPHR_CAP_ST_TABLE_SIZE (PF3_TPHR_CAP_ST_TABLE_SIZE),
    .PF3_TPHR_CAP_VER (PF3_TPHR_CAP_VER),
    .PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 (PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3),
    .PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 (PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2),
    .PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0),
    .PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE),
    .PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP (PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP),
    .PL_DISABLE_RETRAIN_ON_FRAMING_ERROR (PL_DISABLE_RETRAIN_ON_FRAMING_ERROR),
    .PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING),
    .PL_DISABLE_SYNC_HEADER_FRAMING_ERROR (PL_DISABLE_SYNC_HEADER_FRAMING_ERROR),
    .PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE),
    .PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK),
    .PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK),
    .PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT),
    .PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT),
    .PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23),
    .PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT (PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT),
    .PL_EQ_DEFAULT_GEN3_TX_PRESET (PL_EQ_DEFAULT_GEN3_TX_PRESET),
    .PL_EQ_PHASE01_RX_ADAPT (PL_EQ_PHASE01_RX_ADAPT),
    .PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE),
    .PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL),
    .PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL),
    .PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL),
    .PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL),
    .PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL),
    .PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL),
    .PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL),
    .PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL),
    .PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED),
    .PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH),
    .PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1),
    .PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2),
    .PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3),
    .PL_N_FTS_GEN1 (PL_N_FTS_GEN1),
    .PL_N_FTS_GEN2 (PL_N_FTS_GEN2),
    .PL_N_FTS_GEN3 (PL_N_FTS_GEN3),
    .PL_REPORT_ALL_PHY_ERRORS (PL_REPORT_ALL_PHY_ERRORS),
  // synthesis translate_off
    .PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING),
  // synthesis translate_on
    .PL_UPSTREAM_FACING (PL_UPSTREAM_FACING),
    .PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
    .PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY),
    .PM_ENABLE_L23_ENTRY (PM_ENABLE_L23_ENTRY),
    .PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE),
    .PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY),
    .PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY),
    .PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY),
    .SIM_JTAG_IDCODE (SIM_JTAG_IDCODE),
    .SIM_VERSION (SIM_VERSION),
    .SPARE_BIT0 (SPARE_BIT0),
    .SPARE_BIT1 (SPARE_BIT1),
    .SPARE_BIT2 (SPARE_BIT2),
    .SPARE_BIT3 (SPARE_BIT3),
    .SPARE_BIT4 (SPARE_BIT4),
    .SPARE_BIT5 (SPARE_BIT5),
    .SPARE_BIT6 (SPARE_BIT6),
    .SPARE_BIT7 (SPARE_BIT7),
    .SPARE_BIT8 (SPARE_BIT8),
    .SPARE_BYTE0 (SPARE_BYTE0),
    .SPARE_BYTE1 (SPARE_BYTE1),
    .SPARE_BYTE2 (SPARE_BYTE2),
    .SPARE_BYTE3 (SPARE_BYTE3),
    .SPARE_WORD0 (SPARE_WORD0),
    .SPARE_WORD1 (SPARE_WORD1),
    .SPARE_WORD2 (SPARE_WORD2),
    .SPARE_WORD3 (SPARE_WORD3),
    .SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE),
    .TL_COMPLETION_RAM_SIZE_16K (TL_COMPLETION_RAM_SIZE_16K),
    .TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0),
    .TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1),
    .TL_CREDITS_CD (TL_CREDITS_CD),
    .TL_CREDITS_CH (TL_CREDITS_CH),
    .TL_CREDITS_NPD (TL_CREDITS_NPD),
    .TL_CREDITS_NPH (TL_CREDITS_NPH),
    .TL_CREDITS_PD (TL_CREDITS_PD),
    .TL_CREDITS_PH (TL_CREDITS_PH),
    .TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE),
    .TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE),
    .TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE),
    .TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE),
    .TL_PF_ENABLE_REG (TL_PF_ENABLE_REG),
    .TL_TX_MUX_STRICT_PRIORITY (TL_TX_MUX_STRICT_PRIORITY),
    .TWO_LAYER_MODE_DLCMSM_ENABLE (TWO_LAYER_MODE_DLCMSM_ENABLE),
    .TWO_LAYER_MODE_ENABLE (TWO_LAYER_MODE_ENABLE),
    .TWO_LAYER_MODE_WIDTH_256 (TWO_LAYER_MODE_WIDTH_256),
    .VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR),
    .VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER),
    .VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP),
    .VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR),
    .VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET),
    .VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR),
    .VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET),
    .VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE),
    .VF0_PM_CAP_ID (VF0_PM_CAP_ID),
    .VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR),
    .VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID),
    .VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE),
    .VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE),
    .VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR),
    .VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL),
    .VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC),
    .VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE),
    .VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER),
    .VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR),
    .VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP),
    .VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR),
    .VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET),
    .VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR),
    .VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET),
    .VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE),
    .VF1_PM_CAP_ID (VF1_PM_CAP_ID),
    .VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR),
    .VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID),
    .VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE),
    .VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE),
    .VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR),
    .VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL),
    .VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC),
    .VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE),
    .VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER),
    .VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR),
    .VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP),
    .VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR),
    .VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET),
    .VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR),
    .VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET),
    .VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE),
    .VF2_PM_CAP_ID (VF2_PM_CAP_ID),
    .VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR),
    .VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID),
    .VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE),
    .VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE),
    .VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR),
    .VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL),
    .VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC),
    .VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE),
    .VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER),
    .VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR),
    .VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP),
    .VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR),
    .VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET),
    .VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR),
    .VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET),
    .VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE),
    .VF3_PM_CAP_ID (VF3_PM_CAP_ID),
    .VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR),
    .VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID),
    .VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE),
    .VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE),
    .VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR),
    .VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL),
    .VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC),
    .VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE),
    .VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER),
    .VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR),
    .VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP),
    .VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR),
    .VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET),
    .VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR),
    .VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET),
    .VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE),
    .VF4_PM_CAP_ID (VF4_PM_CAP_ID),
    .VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR),
    .VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID),
    .VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE),
    .VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE),
    .VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR),
    .VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL),
    .VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC),
    .VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE),
    .VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER),
    .VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR),
    .VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP),
    .VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR),
    .VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET),
    .VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR),
    .VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET),
    .VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE),
    .VF5_PM_CAP_ID (VF5_PM_CAP_ID),
    .VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR),
    .VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID),
    .VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE),
    .VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE),
    .VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR),
    .VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL),
    .VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC),
    .VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE),
    .VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER),
    .VF6_ARI_CAP_NEXTPTR (VF6_ARI_CAP_NEXTPTR),
    .VF6_MSI_CAP_MULTIMSGCAP (VF6_MSI_CAP_MULTIMSGCAP),
    .VF6_MSIX_CAP_PBA_BIR (VF6_MSIX_CAP_PBA_BIR),
    .VF6_MSIX_CAP_PBA_OFFSET (VF6_MSIX_CAP_PBA_OFFSET),
    .VF6_MSIX_CAP_TABLE_BIR (VF6_MSIX_CAP_TABLE_BIR),
    .VF6_MSIX_CAP_TABLE_OFFSET (VF6_MSIX_CAP_TABLE_OFFSET),
    .VF6_MSIX_CAP_TABLE_SIZE (VF6_MSIX_CAP_TABLE_SIZE),
    .VF6_PM_CAP_ID (VF6_PM_CAP_ID),
    .VF6_PM_CAP_NEXTPTR (VF6_PM_CAP_NEXTPTR),
    .VF6_PM_CAP_VER_ID (VF6_PM_CAP_VER_ID),
    .VF6_TPHR_CAP_DEV_SPECIFIC_MODE (VF6_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF6_TPHR_CAP_ENABLE (VF6_TPHR_CAP_ENABLE),
    .VF6_TPHR_CAP_INT_VEC_MODE (VF6_TPHR_CAP_INT_VEC_MODE),
    .VF6_TPHR_CAP_NEXTPTR (VF6_TPHR_CAP_NEXTPTR),
    .VF6_TPHR_CAP_ST_MODE_SEL (VF6_TPHR_CAP_ST_MODE_SEL),
    .VF6_TPHR_CAP_ST_TABLE_LOC (VF6_TPHR_CAP_ST_TABLE_LOC),
    .VF6_TPHR_CAP_ST_TABLE_SIZE (VF6_TPHR_CAP_ST_TABLE_SIZE),
    .VF6_TPHR_CAP_VER (VF6_TPHR_CAP_VER),
    .VF7_ARI_CAP_NEXTPTR (VF7_ARI_CAP_NEXTPTR),
    .VF7_MSI_CAP_MULTIMSGCAP (VF7_MSI_CAP_MULTIMSGCAP),
    .VF7_MSIX_CAP_PBA_BIR (VF7_MSIX_CAP_PBA_BIR),
    .VF7_MSIX_CAP_PBA_OFFSET (VF7_MSIX_CAP_PBA_OFFSET),
    .VF7_MSIX_CAP_TABLE_BIR (VF7_MSIX_CAP_TABLE_BIR),
    .VF7_MSIX_CAP_TABLE_OFFSET (VF7_MSIX_CAP_TABLE_OFFSET),
    .VF7_MSIX_CAP_TABLE_SIZE (VF7_MSIX_CAP_TABLE_SIZE),
    .VF7_PM_CAP_ID (VF7_PM_CAP_ID),
    .VF7_PM_CAP_NEXTPTR (VF7_PM_CAP_NEXTPTR),
    .VF7_PM_CAP_VER_ID (VF7_PM_CAP_VER_ID),
    .VF7_TPHR_CAP_DEV_SPECIFIC_MODE (VF7_TPHR_CAP_DEV_SPECIFIC_MODE),
    .VF7_TPHR_CAP_ENABLE (VF7_TPHR_CAP_ENABLE),
    .VF7_TPHR_CAP_INT_VEC_MODE (VF7_TPHR_CAP_INT_VEC_MODE),
    .VF7_TPHR_CAP_NEXTPTR (VF7_TPHR_CAP_NEXTPTR),
    .VF7_TPHR_CAP_ST_MODE_SEL (VF7_TPHR_CAP_ST_MODE_SEL),
    .VF7_TPHR_CAP_ST_TABLE_LOC (VF7_TPHR_CAP_ST_TABLE_LOC),
    .VF7_TPHR_CAP_ST_TABLE_SIZE (VF7_TPHR_CAP_ST_TABLE_SIZE),
    .VF7_TPHR_CAP_VER (VF7_TPHR_CAP_VER))
  PCIE_3_1_inst (
    .CFGCONFIGSPACEENABLE (CFGCONFIGSPACEENABLE),
    .CFGDEVID (CFGDEVID),
    .CFGDSBUSNUMBER (CFGDSBUSNUMBER),
    .CFGDSDEVICENUMBER (CFGDSDEVICENUMBER),
    .CFGDSFUNCTIONNUMBER (CFGDSFUNCTIONNUMBER),
    .CFGDSN (CFGDSN),
    .CFGDSPORTNUMBER (CFGDSPORTNUMBER),
    .CFGERRCORIN (CFGERRCORIN),
    .CFGERRUNCORIN (CFGERRUNCORIN),
    .CFGEXTREADDATA (CFGEXTREADDATA),
    .CFGEXTREADDATAVALID (CFGEXTREADDATAVALID),
    .CFGFCSEL (CFGFCSEL),
    .CFGFLRDONE (CFGFLRDONE),
    .CFGHOTRESETIN (CFGHOTRESETIN),
    .CFGINTERRUPTINT (CFGINTERRUPTINT),
    .CFGINTERRUPTMSIATTR (CFGINTERRUPTMSIATTR),
    .CFGINTERRUPTMSIFUNCTIONNUMBER (CFGINTERRUPTMSIFUNCTIONNUMBER),
    .CFGINTERRUPTMSIINT (CFGINTERRUPTMSIINT),
    .CFGINTERRUPTMSIPENDINGSTATUS (CFGINTERRUPTMSIPENDINGSTATUS),
    .CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE (CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE),
    .CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM (CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM),
    .CFGINTERRUPTMSISELECT (CFGINTERRUPTMSISELECT),
    .CFGINTERRUPTMSITPHPRESENT (CFGINTERRUPTMSITPHPRESENT),
    .CFGINTERRUPTMSITPHSTTAG (CFGINTERRUPTMSITPHSTTAG),
    .CFGINTERRUPTMSITPHTYPE (CFGINTERRUPTMSITPHTYPE),
    .CFGINTERRUPTMSIXADDRESS (CFGINTERRUPTMSIXADDRESS),
    .CFGINTERRUPTMSIXDATA (CFGINTERRUPTMSIXDATA),
    .CFGINTERRUPTMSIXINT (CFGINTERRUPTMSIXINT),
    .CFGINTERRUPTPENDING (CFGINTERRUPTPENDING),
    .CFGLINKTRAININGENABLE (CFGLINKTRAININGENABLE),
    .CFGMGMTADDR (CFGMGMTADDR),
    .CFGMGMTBYTEENABLE (CFGMGMTBYTEENABLE),
    .CFGMGMTREAD (CFGMGMTREAD),
    .CFGMGMTTYPE1CFGREGACCESS (CFGMGMTTYPE1CFGREGACCESS),
    .CFGMGMTWRITE (CFGMGMTWRITE),
    .CFGMGMTWRITEDATA (CFGMGMTWRITEDATA),
    .CFGMSGTRANSMIT (CFGMSGTRANSMIT),
    .CFGMSGTRANSMITDATA (CFGMSGTRANSMITDATA),
    .CFGMSGTRANSMITTYPE (CFGMSGTRANSMITTYPE),
    .CFGPERFUNCSTATUSCONTROL (CFGPERFUNCSTATUSCONTROL),
    .CFGPERFUNCTIONNUMBER (CFGPERFUNCTIONNUMBER),
    .CFGPERFUNCTIONOUTPUTREQUEST (CFGPERFUNCTIONOUTPUTREQUEST),
    .CFGPOWERSTATECHANGEACK (CFGPOWERSTATECHANGEACK),
    .CFGREQPMTRANSITIONL23READY (CFGREQPMTRANSITIONL23READY),
    .CFGREVID (CFGREVID),
    .CFGSUBSYSID (CFGSUBSYSID),
    .CFGSUBSYSVENDID (CFGSUBSYSVENDID),
    .CFGTPHSTTREADDATA (CFGTPHSTTREADDATA),
    .CFGTPHSTTREADDATAVALID (CFGTPHSTTREADDATAVALID),
    .CFGVENDID (CFGVENDID),
    .CFGVFFLRDONE (CFGVFFLRDONE),
    .CONFMCAPREQUESTBYCONF (CONFMCAPREQUESTBYCONF),
    .CONFREQDATA (CONFREQDATA),
    .CONFREQREGNUM (CONFREQREGNUM),
    .CONFREQTYPE (CONFREQTYPE),
    .CONFREQVALID (CONFREQVALID),
    .CORECLK (CORECLK),
    .CORECLKMICOMPLETIONRAML (CORECLKMICOMPLETIONRAML),
    .CORECLKMICOMPLETIONRAMU (CORECLKMICOMPLETIONRAMU),
    .CORECLKMIREPLAYRAM (CORECLKMIREPLAYRAM),
    .CORECLKMIREQUESTRAM (CORECLKMIREQUESTRAM),
    .DBGCFGLOCALMGMTREGOVERRIDE (DBGCFGLOCALMGMTREGOVERRIDE),
    .DBGDATASEL (DBGDATASEL),
    .DRPADDR (DRPADDR),
    .DRPCLK (DRPCLK),
    .DRPDI (DRPDI),
    .DRPEN (DRPEN),
    .DRPWE (DRPWE),
    .LL2LMSAXISTXTUSER (LL2LMSAXISTXTUSER),
    .LL2LMSAXISTXTVALID (LL2LMSAXISTXTVALID),
    .LL2LMTXTLPID0 (LL2LMTXTLPID0),
    .LL2LMTXTLPID1 (LL2LMTXTLPID1),
    .MAXISCQTREADY (MAXISCQTREADY),
    .MAXISRCTREADY (MAXISRCTREADY),
    .MCAPCLK (MCAPCLK),
    .MCAPPERST0B (MCAPPERST0B),
    .MCAPPERST1B (MCAPPERST1B),
    .MGMTRESETN (MGMTRESETN),
    .MGMTSTICKYRESETN (MGMTSTICKYRESETN),
    .MICOMPLETIONRAMREADDATA (MICOMPLETIONRAMREADDATA),
    .MIREPLAYRAMREADDATA (MIREPLAYRAMREADDATA),
    .MIREQUESTRAMREADDATA (MIREQUESTRAMREADDATA),
    .PCIECQNPREQ (PCIECQNPREQ),
    .PIPECLK (PIPECLK),
    .PIPEEQFS (PIPEEQFS),
    .PIPEEQLF (PIPEEQLF),
    .PIPERESETN (PIPERESETN),
    .PIPERX0CHARISK (PIPERX0CHARISK),
    .PIPERX0ELECIDLE (PIPERX0ELECIDLE),
    .PIPERX0EQDONE (PIPERX0EQDONE),
    .PIPERX0EQLPADAPTDONE (PIPERX0EQLPADAPTDONE),
    .PIPERX0EQLPLFFSSEL (PIPERX0EQLPLFFSSEL),
    .PIPERX0EQLPNEWTXCOEFFORPRESET (PIPERX0EQLPNEWTXCOEFFORPRESET),
    .PIPERX0PHYSTATUS (PIPERX0PHYSTATUS),
    .PIPERX0VALID (PIPERX0VALID),

    .PIPERX0DATA (PIPERX0DATA_in_int),
    .PIPERX0DATAVALID (PIPERX0DATAVALID_in_int),
    .PIPERX0STARTBLOCK (PIPERX0STARTBLOCK_in_int),
    .PIPERX0STATUS (PIPERX0STATUS_in_int),
    .PIPERX0SYNCHEADER (PIPERX0SYNCHEADER_in_int),

    .PIPERX1CHARISK (PIPERX1CHARISK),
    .PIPERX1ELECIDLE (PIPERX1ELECIDLE),
    .PIPERX1EQDONE (PIPERX1EQDONE),
    .PIPERX1EQLPADAPTDONE (PIPERX1EQLPADAPTDONE),
    .PIPERX1EQLPLFFSSEL (PIPERX1EQLPLFFSSEL),
    .PIPERX1EQLPNEWTXCOEFFORPRESET (PIPERX1EQLPNEWTXCOEFFORPRESET),
    .PIPERX1PHYSTATUS (PIPERX1PHYSTATUS),

    .PIPERX1DATA (PIPERX1DATA_in_int),
    .PIPERX1DATAVALID (PIPERX1DATAVALID_in_int),
    .PIPERX1STARTBLOCK (PIPERX1STARTBLOCK_in_int),
    .PIPERX1STATUS (PIPERX1STATUS_in_int),
    .PIPERX1SYNCHEADER (PIPERX1SYNCHEADER_in_int),

    .PIPERX1VALID (PIPERX1VALID),
    .PIPERX2CHARISK (PIPERX2CHARISK),
    .PIPERX2ELECIDLE (PIPERX2ELECIDLE),
    .PIPERX2EQDONE (PIPERX2EQDONE),
    .PIPERX2EQLPADAPTDONE (PIPERX2EQLPADAPTDONE),
    .PIPERX2EQLPLFFSSEL (PIPERX2EQLPLFFSSEL),
    .PIPERX2EQLPNEWTXCOEFFORPRESET (PIPERX2EQLPNEWTXCOEFFORPRESET),
    .PIPERX2PHYSTATUS (PIPERX2PHYSTATUS),

    .PIPERX2DATA (PIPERX2DATA_in_int),
    .PIPERX2DATAVALID (PIPERX2DATAVALID_in_int),
    .PIPERX2STARTBLOCK (PIPERX2STARTBLOCK_in_int),
    .PIPERX2STATUS (PIPERX2STATUS_in_int),
    .PIPERX2SYNCHEADER (PIPERX2SYNCHEADER_in_int),

    .PIPERX2VALID (PIPERX2VALID),
    .PIPERX3CHARISK (PIPERX3CHARISK),
    .PIPERX3ELECIDLE (PIPERX3ELECIDLE),
    .PIPERX3EQDONE (PIPERX3EQDONE),
    .PIPERX3EQLPADAPTDONE (PIPERX3EQLPADAPTDONE),
    .PIPERX3EQLPLFFSSEL (PIPERX3EQLPLFFSSEL),
    .PIPERX3EQLPNEWTXCOEFFORPRESET (PIPERX3EQLPNEWTXCOEFFORPRESET),
    .PIPERX3PHYSTATUS (PIPERX3PHYSTATUS),

    .PIPERX3DATA (PIPERX3DATA_in_int),
    .PIPERX3DATAVALID (PIPERX3DATAVALID_in_int),
    .PIPERX3STARTBLOCK (PIPERX3STARTBLOCK_in_int),
    .PIPERX3STATUS (PIPERX3STATUS_in_int),
    .PIPERX3SYNCHEADER (PIPERX3SYNCHEADER_in_int),

    .PIPERX3VALID (PIPERX3VALID),
    .PIPERX4CHARISK (PIPERX4CHARISK),
    .PIPERX4ELECIDLE (PIPERX4ELECIDLE),
    .PIPERX4EQDONE (PIPERX4EQDONE),
    .PIPERX4EQLPADAPTDONE (PIPERX4EQLPADAPTDONE),
    .PIPERX4EQLPLFFSSEL (PIPERX4EQLPLFFSSEL),
    .PIPERX4EQLPNEWTXCOEFFORPRESET (PIPERX4EQLPNEWTXCOEFFORPRESET),
    .PIPERX4PHYSTATUS (PIPERX4PHYSTATUS),

    .PIPERX4DATA (PIPERX4DATA_in_int),
    .PIPERX4DATAVALID (PIPERX4DATAVALID_in_int),
    .PIPERX4STARTBLOCK (PIPERX4STARTBLOCK_in_int),
    .PIPERX4STATUS (PIPERX4STATUS_in_int),
    .PIPERX4SYNCHEADER (PIPERX4SYNCHEADER_in_int),

    .PIPERX4VALID (PIPERX4VALID),
    .PIPERX5CHARISK (PIPERX5CHARISK),
    .PIPERX5ELECIDLE (PIPERX5ELECIDLE),
    .PIPERX5EQDONE (PIPERX5EQDONE),
    .PIPERX5EQLPADAPTDONE (PIPERX5EQLPADAPTDONE),
    .PIPERX5EQLPLFFSSEL (PIPERX5EQLPLFFSSEL),
    .PIPERX5EQLPNEWTXCOEFFORPRESET (PIPERX5EQLPNEWTXCOEFFORPRESET),
    .PIPERX5PHYSTATUS (PIPERX5PHYSTATUS),

    .PIPERX5DATA (PIPERX5DATA_in_int),
    .PIPERX5DATAVALID (PIPERX5DATAVALID_in_int),
    .PIPERX5STARTBLOCK (PIPERX5STARTBLOCK_in_int),
    .PIPERX5STATUS (PIPERX5STATUS_in_int),
    .PIPERX5SYNCHEADER (PIPERX5SYNCHEADER_in_int),

    .PIPERX5VALID (PIPERX5VALID),
    .PIPERX6CHARISK (PIPERX6CHARISK),
    .PIPERX6ELECIDLE (PIPERX6ELECIDLE),
    .PIPERX6EQDONE (PIPERX6EQDONE),
    .PIPERX6EQLPADAPTDONE (PIPERX6EQLPADAPTDONE),
    .PIPERX6EQLPLFFSSEL (PIPERX6EQLPLFFSSEL),
    .PIPERX6EQLPNEWTXCOEFFORPRESET (PIPERX6EQLPNEWTXCOEFFORPRESET),
    .PIPERX6PHYSTATUS (PIPERX6PHYSTATUS),

    .PIPERX6DATA (PIPERX6DATA_in_int),
    .PIPERX6DATAVALID (PIPERX6DATAVALID_in_int),
    .PIPERX6STARTBLOCK (PIPERX6STARTBLOCK_in_int),
    .PIPERX6STATUS (PIPERX6STATUS_in_int),
    .PIPERX6SYNCHEADER (PIPERX6SYNCHEADER_in_int),

    .PIPERX6VALID (PIPERX6VALID),
    .PIPERX7CHARISK (PIPERX7CHARISK),
    .PIPERX7ELECIDLE (PIPERX7ELECIDLE),
    .PIPERX7EQDONE (PIPERX7EQDONE),
    .PIPERX7EQLPADAPTDONE (PIPERX7EQLPADAPTDONE),
    .PIPERX7EQLPLFFSSEL (PIPERX7EQLPLFFSSEL),
    .PIPERX7EQLPNEWTXCOEFFORPRESET (PIPERX7EQLPNEWTXCOEFFORPRESET),
    .PIPERX7PHYSTATUS (PIPERX7PHYSTATUS),

    .PIPERX7DATA (PIPERX7DATA_in_int),
    .PIPERX7DATAVALID (PIPERX7DATAVALID_in_int),
    .PIPERX7STARTBLOCK (PIPERX7STARTBLOCK_in_int),
    .PIPERX7STATUS (PIPERX7STATUS_in_int),
    .PIPERX7SYNCHEADER (PIPERX7SYNCHEADER_in_int),

    .PIPERX7VALID (PIPERX7VALID),
    .PIPETX0EQCOEFF (PIPETX0EQCOEFF),
    .PIPETX0EQDONE (PIPETX0EQDONE),
    .PIPETX1EQCOEFF (PIPETX1EQCOEFF),
    .PIPETX1EQDONE (PIPETX1EQDONE),
    .PIPETX2EQCOEFF (PIPETX2EQCOEFF),
    .PIPETX2EQDONE (PIPETX2EQDONE),
    .PIPETX3EQCOEFF (PIPETX3EQCOEFF),
    .PIPETX3EQDONE (PIPETX3EQDONE),
    .PIPETX4EQCOEFF (PIPETX4EQCOEFF),
    .PIPETX4EQDONE (PIPETX4EQDONE),
    .PIPETX5EQCOEFF (PIPETX5EQCOEFF),
    .PIPETX5EQDONE (PIPETX5EQDONE),
    .PIPETX6EQCOEFF (PIPETX6EQCOEFF),
    .PIPETX6EQDONE (PIPETX6EQDONE),
    .PIPETX7EQCOEFF (PIPETX7EQCOEFF),
    .PIPETX7EQDONE (PIPETX7EQDONE),
    .PLEQRESETEIEOSCOUNT (PLEQRESETEIEOSCOUNT),
    .PLGEN2UPSTREAMPREFERDEEMPH (PLGEN2UPSTREAMPREFERDEEMPH),
    .RESETN (RESETN),
    .SAXISCCTDATA (SAXISCCTDATA),
    .SAXISCCTKEEP (SAXISCCTKEEP),
    .SAXISCCTLAST (SAXISCCTLAST),
    .SAXISCCTUSER (SAXISCCTUSER),
    .SAXISCCTVALID (SAXISCCTVALID),
    .SAXISRQTDATA (SAXISRQTDATA),
    .SAXISRQTKEEP (SAXISRQTKEEP),
    .SAXISRQTLAST (SAXISRQTLAST),
    .SAXISRQTUSER (SAXISRQTUSER),
    .SAXISRQTVALID (SAXISRQTVALID),
    .SPAREIN (SPAREIN),
    .USERCLK (USERCLK),
    .CFGCURRENTSPEED (CFGCURRENTSPEED),
    .CFGDPASUBSTATECHANGE (CFGDPASUBSTATECHANGE),
    .CFGERRCOROUT (CFGERRCOROUT),
    .CFGERRFATALOUT (CFGERRFATALOUT),
    .CFGERRNONFATALOUT (CFGERRNONFATALOUT),
    .CFGEXTFUNCTIONNUMBER (CFGEXTFUNCTIONNUMBER),
    .CFGEXTREADRECEIVED (CFGEXTREADRECEIVED),
    .CFGEXTREGISTERNUMBER (CFGEXTREGISTERNUMBER),
    .CFGEXTWRITEBYTEENABLE (CFGEXTWRITEBYTEENABLE),
    .CFGEXTWRITEDATA (CFGEXTWRITEDATA),
    .CFGEXTWRITERECEIVED (CFGEXTWRITERECEIVED),
    .CFGFCCPLD (CFGFCCPLD),
    .CFGFCCPLH (CFGFCCPLH),
    .CFGFCNPD (CFGFCNPD),
    .CFGFCNPH (CFGFCNPH),
    .CFGFCPD (CFGFCPD),
    .CFGFCPH (CFGFCPH),
    .CFGFLRINPROCESS (CFGFLRINPROCESS),
    .CFGFUNCTIONPOWERSTATE (CFGFUNCTIONPOWERSTATE),
    .CFGFUNCTIONSTATUS (CFGFUNCTIONSTATUS),
    .CFGHOTRESETOUT (CFGHOTRESETOUT),
    .CFGINTERRUPTMSIDATA (CFGINTERRUPTMSIDATA),
    .CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE),
    .CFGINTERRUPTMSIFAIL (CFGINTERRUPTMSIFAIL),
    .CFGINTERRUPTMSIMASKUPDATE (CFGINTERRUPTMSIMASKUPDATE),
    .CFGINTERRUPTMSIMMENABLE (CFGINTERRUPTMSIMMENABLE),
    .CFGINTERRUPTMSISENT (CFGINTERRUPTMSISENT),
    .CFGINTERRUPTMSIVFENABLE (CFGINTERRUPTMSIVFENABLE),
    .CFGINTERRUPTMSIXENABLE (CFGINTERRUPTMSIXENABLE),
    .CFGINTERRUPTMSIXFAIL (CFGINTERRUPTMSIXFAIL),
    .CFGINTERRUPTMSIXMASK (CFGINTERRUPTMSIXMASK),
    .CFGINTERRUPTMSIXSENT (CFGINTERRUPTMSIXSENT),
    .CFGINTERRUPTMSIXVFENABLE (CFGINTERRUPTMSIXVFENABLE),
    .CFGINTERRUPTMSIXVFMASK (CFGINTERRUPTMSIXVFMASK),
    .CFGINTERRUPTSENT (CFGINTERRUPTSENT),
    .CFGLINKPOWERSTATE (CFGLINKPOWERSTATE),
    .CFGLOCALERROR (CFGLOCALERROR),
    .CFGLTRENABLE (CFGLTRENABLE),
    .CFGLTSSMSTATE (CFGLTSSMSTATE),
    .CFGMAXPAYLOAD (CFGMAXPAYLOAD),
    .CFGMAXREADREQ (CFGMAXREADREQ),
    .CFGMGMTREADDATA (CFGMGMTREADDATA),
    .CFGMGMTREADWRITEDONE (CFGMGMTREADWRITEDONE),
    .CFGMSGRECEIVED (CFGMSGRECEIVED),
    .CFGMSGRECEIVEDDATA (CFGMSGRECEIVEDDATA),
    .CFGMSGRECEIVEDTYPE (CFGMSGRECEIVEDTYPE),
    .CFGMSGTRANSMITDONE (CFGMSGTRANSMITDONE),
    .CFGNEGOTIATEDWIDTH (CFGNEGOTIATEDWIDTH),
    .CFGOBFFENABLE (CFGOBFFENABLE),
    .CFGPERFUNCSTATUSDATA (CFGPERFUNCSTATUSDATA),
    .CFGPERFUNCTIONUPDATEDONE (CFGPERFUNCTIONUPDATEDONE),
    .CFGPHYLINKDOWN (CFGPHYLINKDOWN),
    .CFGPHYLINKSTATUS (CFGPHYLINKSTATUS),
    .CFGPLSTATUSCHANGE (CFGPLSTATUSCHANGE),
    .CFGPOWERSTATECHANGEINTERRUPT (CFGPOWERSTATECHANGEINTERRUPT),
    .CFGRCBSTATUS (CFGRCBSTATUS),
    .CFGTPHFUNCTIONNUM (CFGTPHFUNCTIONNUM),
    .CFGTPHREQUESTERENABLE (CFGTPHREQUESTERENABLE),
    .CFGTPHSTMODE (CFGTPHSTMODE),
    .CFGTPHSTTADDRESS (CFGTPHSTTADDRESS),
    .CFGTPHSTTREADENABLE (CFGTPHSTTREADENABLE),
    .CFGTPHSTTWRITEBYTEVALID (CFGTPHSTTWRITEBYTEVALID),
    .CFGTPHSTTWRITEDATA (CFGTPHSTTWRITEDATA),
    .CFGTPHSTTWRITEENABLE (CFGTPHSTTWRITEENABLE),
    .CFGVFFLRINPROCESS (CFGVFFLRINPROCESS),
    .CFGVFPOWERSTATE (CFGVFPOWERSTATE),
    .CFGVFSTATUS (CFGVFSTATUS),
    .CFGVFTPHREQUESTERENABLE (CFGVFTPHREQUESTERENABLE),
    .CFGVFTPHSTMODE (CFGVFTPHSTMODE),
    .CONFMCAPDESIGNSWITCH (CONFMCAPDESIGNSWITCH),
    .CONFMCAPEOS (CONFMCAPEOS),
    .CONFMCAPINUSEBYPCIE (CONFMCAPINUSEBYPCIE),
    .CONFREQREADY (CONFREQREADY),
    .CONFRESPRDATA (CONFRESPRDATA),
    .CONFRESPVALID (CONFRESPVALID),
    .DBGDATAOUT (DBGDATAOUT),
    .DBGMCAPCSB (DBGMCAPCSB),
    .DBGMCAPDATA (DBGMCAPDATA),
    .DBGMCAPEOS (DBGMCAPEOS),
    .DBGMCAPERROR (DBGMCAPERROR),
    .DBGMCAPMODE (DBGMCAPMODE),
    .DBGMCAPRDATAVALID (DBGMCAPRDATAVALID),
    .DBGMCAPRDWRB (DBGMCAPRDWRB),
    .DBGMCAPRESET (DBGMCAPRESET),
    .DBGPLDATABLOCKRECEIVEDAFTEREDS (DBGPLDATABLOCKRECEIVEDAFTEREDS),
    .DBGPLGEN3FRAMINGERRORDETECTED (DBGPLGEN3FRAMINGERRORDETECTED),
    .DBGPLGEN3SYNCHEADERERRORDETECTED (DBGPLGEN3SYNCHEADERERRORDETECTED),
    .DBGPLINFERREDRXELECTRICALIDLE (DBGPLINFERREDRXELECTRICALIDLE),
    .DRPDO (DRPDO),
    .DRPRDY (DRPRDY),
    .LL2LMMASTERTLPSENTTLPID0 (LL2LMMASTERTLPSENTTLPID0),
    .LL2LMMASTERTLPSENTTLPID1 (LL2LMMASTERTLPSENTTLPID1),
    .LL2LMMASTERTLPSENT0 (LL2LMMASTERTLPSENT0),
    .LL2LMMASTERTLPSENT1 (LL2LMMASTERTLPSENT1),
    .LL2LMMAXISRXTDATA (LL2LMMAXISRXTDATA),
    .LL2LMMAXISRXTUSER (LL2LMMAXISRXTUSER),
    .LL2LMMAXISRXTVALID (LL2LMMAXISRXTVALID),
    .LL2LMSAXISTXTREADY (LL2LMSAXISTXTREADY),
    .MAXISCQTDATA (  MAXISCQTDATA_i ),
    .MAXISCQTKEEP (  MAXISCQTKEEP_i ),
    .MAXISCQTLAST (  MAXISCQTLAST_i ),
    .MAXISCQTUSER (  MAXISCQTUSER_i ),
    .MAXISCQTVALID ( MAXISCQTVALID_i ),
    .MAXISRCTDATA (MAXISRCTDATA),
    .MAXISRCTKEEP (MAXISRCTKEEP),
    .MAXISRCTLAST (MAXISRCTLAST),
    .MAXISRCTUSER (MAXISRCTUSER),
    .MAXISRCTVALID (MAXISRCTVALID),
    .MICOMPLETIONRAMREADADDRESSAL (MICOMPLETIONRAMREADADDRESSAL),
    .MICOMPLETIONRAMREADADDRESSAU (MICOMPLETIONRAMREADADDRESSAU),
    .MICOMPLETIONRAMREADADDRESSBL (MICOMPLETIONRAMREADADDRESSBL),
    .MICOMPLETIONRAMREADADDRESSBU (MICOMPLETIONRAMREADADDRESSBU),
    .MICOMPLETIONRAMREADENABLEL (MICOMPLETIONRAMREADENABLEL),
    .MICOMPLETIONRAMREADENABLEU (MICOMPLETIONRAMREADENABLEU),
    .MICOMPLETIONRAMWRITEADDRESSAL (MICOMPLETIONRAMWRITEADDRESSAL),
    .MICOMPLETIONRAMWRITEADDRESSAU (MICOMPLETIONRAMWRITEADDRESSAU),
    .MICOMPLETIONRAMWRITEADDRESSBL (MICOMPLETIONRAMWRITEADDRESSBL),
    .MICOMPLETIONRAMWRITEADDRESSBU (MICOMPLETIONRAMWRITEADDRESSBU),
    .MICOMPLETIONRAMWRITEDATAL (MICOMPLETIONRAMWRITEDATAL),
    .MICOMPLETIONRAMWRITEDATAU (MICOMPLETIONRAMWRITEDATAU),
    .MICOMPLETIONRAMWRITEENABLEL (MICOMPLETIONRAMWRITEENABLEL),
    .MICOMPLETIONRAMWRITEENABLEU (MICOMPLETIONRAMWRITEENABLEU),
    .MIREPLAYRAMADDRESS (MIREPLAYRAMADDRESS),
    .MIREPLAYRAMREADENABLE (MIREPLAYRAMREADENABLE),
    .MIREPLAYRAMWRITEDATA (MIREPLAYRAMWRITEDATA),
    .MIREPLAYRAMWRITEENABLE (MIREPLAYRAMWRITEENABLE),
    .MIREQUESTRAMREADADDRESSA (MIREQUESTRAMREADADDRESSA),
    .MIREQUESTRAMREADADDRESSB (MIREQUESTRAMREADADDRESSB),
    .MIREQUESTRAMREADENABLE (MIREQUESTRAMREADENABLE),
    .MIREQUESTRAMWRITEADDRESSA (MIREQUESTRAMWRITEADDRESSA),
    .MIREQUESTRAMWRITEADDRESSB (MIREQUESTRAMWRITEADDRESSB),
    .MIREQUESTRAMWRITEDATA (MIREQUESTRAMWRITEDATA),
    .MIREQUESTRAMWRITEENABLE (MIREQUESTRAMWRITEENABLE),
    .PCIECQNPREQCOUNT (PCIECQNPREQCOUNT),
    .PCIEPERST0B (PCIEPERST0B),
    .PCIEPERST1B (PCIEPERST1B),
    .PCIERQSEQNUM (PCIERQSEQNUM),
    .PCIERQSEQNUMVLD (PCIERQSEQNUMVLD),
    .PCIERQTAG (PCIERQTAG),
    .PCIERQTAGAV (PCIERQTAGAV),
    .PCIERQTAGVLD (PCIERQTAGVLD),
    .PCIETFCNPDAV (PCIETFCNPDAV),
    .PCIETFCNPHAV (PCIETFCNPHAV),
    .PIPERX0EQCONTROL (PIPERX0EQCONTROL),
    .PIPERX0EQLPLFFS (PIPERX0EQLPLFFS),
    .PIPERX0EQLPTXPRESET (PIPERX0EQLPTXPRESET),
    .PIPERX0EQPRESET (PIPERX0EQPRESET),
    .PIPERX0POLARITY (PIPERX0POLARITY),
    .PIPERX1EQCONTROL (PIPERX1EQCONTROL),
    .PIPERX1EQLPLFFS (PIPERX1EQLPLFFS),
    .PIPERX1EQLPTXPRESET (PIPERX1EQLPTXPRESET),
    .PIPERX1EQPRESET (PIPERX1EQPRESET),
    .PIPERX1POLARITY (PIPERX1POLARITY),
    .PIPERX2EQCONTROL (PIPERX2EQCONTROL),
    .PIPERX2EQLPLFFS (PIPERX2EQLPLFFS),
    .PIPERX2EQLPTXPRESET (PIPERX2EQLPTXPRESET),
    .PIPERX2EQPRESET (PIPERX2EQPRESET),
    .PIPERX2POLARITY (PIPERX2POLARITY),
    .PIPERX3EQCONTROL (PIPERX3EQCONTROL),
    .PIPERX3EQLPLFFS (PIPERX3EQLPLFFS),
    .PIPERX3EQLPTXPRESET (PIPERX3EQLPTXPRESET),
    .PIPERX3EQPRESET (PIPERX3EQPRESET),
    .PIPERX3POLARITY (PIPERX3POLARITY),
    .PIPERX4EQCONTROL (PIPERX4EQCONTROL),
    .PIPERX4EQLPLFFS (PIPERX4EQLPLFFS),
    .PIPERX4EQLPTXPRESET (PIPERX4EQLPTXPRESET),
    .PIPERX4EQPRESET (PIPERX4EQPRESET),
    .PIPERX4POLARITY (PIPERX4POLARITY),
    .PIPERX5EQCONTROL (PIPERX5EQCONTROL),
    .PIPERX5EQLPLFFS (PIPERX5EQLPLFFS),
    .PIPERX5EQLPTXPRESET (PIPERX5EQLPTXPRESET),
    .PIPERX5EQPRESET (PIPERX5EQPRESET),
    .PIPERX5POLARITY (PIPERX5POLARITY),
    .PIPERX6EQCONTROL (PIPERX6EQCONTROL),
    .PIPERX6EQLPLFFS (PIPERX6EQLPLFFS),
    .PIPERX6EQLPTXPRESET (PIPERX6EQLPTXPRESET),
    .PIPERX6EQPRESET (PIPERX6EQPRESET),
    .PIPERX6POLARITY (PIPERX6POLARITY),
    .PIPERX7EQCONTROL (PIPERX7EQCONTROL),
    .PIPERX7EQLPLFFS (PIPERX7EQLPLFFS),
    .PIPERX7EQLPTXPRESET (PIPERX7EQLPTXPRESET),
    .PIPERX7EQPRESET (PIPERX7EQPRESET),
    .PIPERX7POLARITY (PIPERX7POLARITY),
    .PIPETX0CHARISK (PIPETX0CHARISK),
    .PIPETX0COMPLIANCE (PIPETX0COMPLIANCE),
    .PIPETX0DATA (PIPETX0DATA),
    .PIPETX0DATAVALID (PIPETX0DATAVALID),
    .PIPETX0DEEMPH (PIPETX0DEEMPH),
    .PIPETX0ELECIDLE (PIPETX0ELECIDLE),
    .PIPETX0EQCONTROL (PIPETX0EQCONTROL),
    .PIPETX0EQDEEMPH (PIPETX0EQDEEMPH),
    .PIPETX0EQPRESET (PIPETX0EQPRESET),
    .PIPETX0MARGIN (PIPETX0MARGIN),
    .PIPETX0POWERDOWN (PIPETX0POWERDOWN),
    .PIPETX0RATE (PIPETX0RATE),
    .PIPETX0RCVRDET (PIPETX0RCVRDET),
    .PIPETX0RESET (PIPETX0RESET),
    .PIPETX0STARTBLOCK (PIPETX0STARTBLOCK),
    .PIPETX0SWING (PIPETX0SWING),
    .PIPETX0SYNCHEADER (PIPETX0SYNCHEADER),
    .PIPETX1CHARISK (PIPETX1CHARISK),
    .PIPETX1COMPLIANCE (PIPETX1COMPLIANCE),
    .PIPETX1DATA (PIPETX1DATA),
    .PIPETX1DATAVALID (PIPETX1DATAVALID),
    .PIPETX1DEEMPH (PIPETX1DEEMPH),
    .PIPETX1ELECIDLE (PIPETX1ELECIDLE),
    .PIPETX1EQCONTROL (PIPETX1EQCONTROL),
    .PIPETX1EQDEEMPH (PIPETX1EQDEEMPH),
    .PIPETX1EQPRESET (PIPETX1EQPRESET),
    .PIPETX1MARGIN (PIPETX1MARGIN),
    .PIPETX1POWERDOWN (PIPETX1POWERDOWN),
    .PIPETX1RATE (PIPETX1RATE),
    .PIPETX1RCVRDET (PIPETX1RCVRDET),
    .PIPETX1RESET (PIPETX1RESET),
    .PIPETX1STARTBLOCK (PIPETX1STARTBLOCK),
    .PIPETX1SWING (PIPETX1SWING),
    .PIPETX1SYNCHEADER (PIPETX1SYNCHEADER),
    .PIPETX2CHARISK (PIPETX2CHARISK),
    .PIPETX2COMPLIANCE (PIPETX2COMPLIANCE),
    .PIPETX2DATA (PIPETX2DATA),
    .PIPETX2DATAVALID (PIPETX2DATAVALID),
    .PIPETX2DEEMPH (PIPETX2DEEMPH),
    .PIPETX2ELECIDLE (PIPETX2ELECIDLE),
    .PIPETX2EQCONTROL (PIPETX2EQCONTROL),
    .PIPETX2EQDEEMPH (PIPETX2EQDEEMPH),
    .PIPETX2EQPRESET (PIPETX2EQPRESET),
    .PIPETX2MARGIN (PIPETX2MARGIN),
    .PIPETX2POWERDOWN (PIPETX2POWERDOWN),
    .PIPETX2RATE (PIPETX2RATE),
    .PIPETX2RCVRDET (PIPETX2RCVRDET),
    .PIPETX2RESET (PIPETX2RESET),
    .PIPETX2STARTBLOCK (PIPETX2STARTBLOCK),
    .PIPETX2SWING (PIPETX2SWING),
    .PIPETX2SYNCHEADER (PIPETX2SYNCHEADER),
    .PIPETX3CHARISK (PIPETX3CHARISK),
    .PIPETX3COMPLIANCE (PIPETX3COMPLIANCE),
    .PIPETX3DATA (PIPETX3DATA),
    .PIPETX3DATAVALID (PIPETX3DATAVALID),
    .PIPETX3DEEMPH (PIPETX3DEEMPH),
    .PIPETX3ELECIDLE (PIPETX3ELECIDLE),
    .PIPETX3EQCONTROL (PIPETX3EQCONTROL),
    .PIPETX3EQDEEMPH (PIPETX3EQDEEMPH),
    .PIPETX3EQPRESET (PIPETX3EQPRESET),
    .PIPETX3MARGIN (PIPETX3MARGIN),
    .PIPETX3POWERDOWN (PIPETX3POWERDOWN),
    .PIPETX3RATE (PIPETX3RATE),
    .PIPETX3RCVRDET (PIPETX3RCVRDET),
    .PIPETX3RESET (PIPETX3RESET),
    .PIPETX3STARTBLOCK (PIPETX3STARTBLOCK),
    .PIPETX3SWING (PIPETX3SWING),
    .PIPETX3SYNCHEADER (PIPETX3SYNCHEADER),
    .PIPETX4CHARISK (PIPETX4CHARISK),
    .PIPETX4COMPLIANCE (PIPETX4COMPLIANCE),
    .PIPETX4DATA (PIPETX4DATA),
    .PIPETX4DATAVALID (PIPETX4DATAVALID),
    .PIPETX4DEEMPH (PIPETX4DEEMPH),
    .PIPETX4ELECIDLE (PIPETX4ELECIDLE),
    .PIPETX4EQCONTROL (PIPETX4EQCONTROL),
    .PIPETX4EQDEEMPH (PIPETX4EQDEEMPH),
    .PIPETX4EQPRESET (PIPETX4EQPRESET),
    .PIPETX4MARGIN (PIPETX4MARGIN),
    .PIPETX4POWERDOWN (PIPETX4POWERDOWN),
    .PIPETX4RATE (PIPETX4RATE),
    .PIPETX4RCVRDET (PIPETX4RCVRDET),
    .PIPETX4RESET (PIPETX4RESET),
    .PIPETX4STARTBLOCK (PIPETX4STARTBLOCK),
    .PIPETX4SWING (PIPETX4SWING),
    .PIPETX4SYNCHEADER (PIPETX4SYNCHEADER),
    .PIPETX5CHARISK (PIPETX5CHARISK),
    .PIPETX5COMPLIANCE (PIPETX5COMPLIANCE),
    .PIPETX5DATA (PIPETX5DATA),
    .PIPETX5DATAVALID (PIPETX5DATAVALID),
    .PIPETX5DEEMPH (PIPETX5DEEMPH),
    .PIPETX5ELECIDLE (PIPETX5ELECIDLE),
    .PIPETX5EQCONTROL (PIPETX5EQCONTROL),
    .PIPETX5EQDEEMPH (PIPETX5EQDEEMPH),
    .PIPETX5EQPRESET (PIPETX5EQPRESET),
    .PIPETX5MARGIN (PIPETX5MARGIN),
    .PIPETX5POWERDOWN (PIPETX5POWERDOWN),
    .PIPETX5RATE (PIPETX5RATE),
    .PIPETX5RCVRDET (PIPETX5RCVRDET),
    .PIPETX5RESET (PIPETX5RESET),
    .PIPETX5STARTBLOCK (PIPETX5STARTBLOCK),
    .PIPETX5SWING (PIPETX5SWING),
    .PIPETX5SYNCHEADER (PIPETX5SYNCHEADER),
    .PIPETX6CHARISK (PIPETX6CHARISK),
    .PIPETX6COMPLIANCE (PIPETX6COMPLIANCE),
    .PIPETX6DATA (PIPETX6DATA),
    .PIPETX6DATAVALID (PIPETX6DATAVALID),
    .PIPETX6DEEMPH (PIPETX6DEEMPH),
    .PIPETX6ELECIDLE (PIPETX6ELECIDLE),
    .PIPETX6EQCONTROL (PIPETX6EQCONTROL),
    .PIPETX6EQDEEMPH (PIPETX6EQDEEMPH),
    .PIPETX6EQPRESET (PIPETX6EQPRESET),
    .PIPETX6MARGIN (PIPETX6MARGIN),
    .PIPETX6POWERDOWN (PIPETX6POWERDOWN),
    .PIPETX6RATE (PIPETX6RATE),
    .PIPETX6RCVRDET (PIPETX6RCVRDET),
    .PIPETX6RESET (PIPETX6RESET),
    .PIPETX6STARTBLOCK (PIPETX6STARTBLOCK),
    .PIPETX6SWING (PIPETX6SWING),
    .PIPETX6SYNCHEADER (PIPETX6SYNCHEADER),
    .PIPETX7CHARISK (PIPETX7CHARISK),
    .PIPETX7COMPLIANCE (PIPETX7COMPLIANCE),
    .PIPETX7DATA (PIPETX7DATA),
    .PIPETX7DATAVALID (PIPETX7DATAVALID),
    .PIPETX7DEEMPH (PIPETX7DEEMPH),
    .PIPETX7ELECIDLE (PIPETX7ELECIDLE),
    .PIPETX7EQCONTROL (PIPETX7EQCONTROL),
    .PIPETX7EQDEEMPH (PIPETX7EQDEEMPH),
    .PIPETX7EQPRESET (PIPETX7EQPRESET),
    .PIPETX7MARGIN (PIPETX7MARGIN),
    .PIPETX7POWERDOWN (PIPETX7POWERDOWN),
    .PIPETX7RATE (PIPETX7RATE),
    .PIPETX7RCVRDET (PIPETX7RCVRDET),
    .PIPETX7RESET (PIPETX7RESET),
    .PIPETX7STARTBLOCK (PIPETX7STARTBLOCK),
    .PIPETX7SWING (PIPETX7SWING),
    .PIPETX7SYNCHEADER (PIPETX7SYNCHEADER),
    .PLEQINPROGRESS (PLEQINPROGRESS),
    .PLEQPHASE (PLEQPHASE),
    .SAXISCCTREADY (SAXISCCTREADY),
    .SAXISRQTREADY (SAXISRQTREADY),
    .SPAREOUT (SPAREOUT)
  );



   assign  MAXISCQTDATA  = MAXISCQTDATA_i;
   assign  MAXISCQTKEEP  = MAXISCQTKEEP_i;
   assign  MAXISCQTLAST  = MAXISCQTLAST_i;
   assign  MAXISCQTUSER  = MAXISCQTUSER_i;
   assign  MAXISCQTVALID = MAXISCQTVALID_i;


endmodule
